Gaku Minamihaba

Self‐aligned passivation on copper interconnection durability against oxidizing ambient annealing

A self‐aligned niobium (Nb) passivation method has been developed in order to improve the stability of copper (Cu) in an oxidizing ambient. A Cu/Nb/SiO2/(100)Si structure was annealed between 400 and 850 °C for 30 min in a gas mixture of H2 and N2. The underlying Nb diffused to the Cu surface and turned into its nitride at 750 °C. The surface Nb nitride layer acted as a passivation layer against oxidation. The passivated Cu was found to retain its resistivity of 2.0 μΩ cm even after oxidation at 400 °C for 30 min in a dry oxygen ambient.

High-performance CMP Slurry with Inorganic/Resin Abrasive for Al/Low k Damascene

CMP slurry with inorganic/resin abrasive was investigated for the Al/low k damascene wiring. [1] The slurry showed less scratching, higher polishing rate and better planarity. These advantages are attributable to the elasticity of the resin. The soft resin particle behaves as a cushion and prevents the scratching caused by agglomerated inorganic particles and foreign material. The springy feature of the resin particle increases the selectivity of removal rate at convex portions and concave portions. Furthermore, the pressure is loaded to the Al film surface effectively through the resin particle and higher CMP rate can be achieved even without chemicals such as oxidizers and acids. [2] This chemical free polishing would be the advantageous for preventing the corrosion of Al.

Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric

Self-formed barrier technology using copper (Cu) manganese (Mn) alloy seed was applied for Cu dual-damascene interconnect with porous-SiOC/porous-PAr (k=2.3) hybrid dielectric for the first time. More than 90% yield for wiring and via-chain was obtained. 70% reduction in via resistance was confirmed compared with the conventional process. To estimate the moisture resistance property of self-formed barrier, via resistance change was measured with dummy density pattern. As the result, it was found that the resistance change ratio of via for self-formed barrier does not depend on the dummy density, probably due to the high moisture resistance property of self-formed oxide barrier. In addition, outgas at high temperature is found to be essential to form self-formed barrier for porous dielectric.

Low Leakage TiO2 Gate Insulator Formed by Ultrathin TiN Deposition and Low-Temperature Oxidation

A new method of forming TiO2 gate insulators is proposed. It was found that ultrathin TiN deposition on ultrathin SiO2 and low-temperature thermal oxidation resulted in smaller TiO2 grains surrounded by amorphous boundaries. The gate leakage current was effectively reduced by applying ultrathin TiO2/SiO2 stacked insulators to metal-oxide-semiconductor (MOS) capacitors and Damascene gate metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with good characteristics were successfully fabricated.

Double-Level Cu Inlaid Interconnects with Simultaneously Filled Via Plugs

A double-level Cu interconnection process for lower submicron generation ULSIs was developed. Cu interconnects were successfully formed by Cu/WSiN sputtering, XeCl excimer laser annealing and Cu/WSiN chemical mechanical polishing. The composition of the WSiN barrier metal was optimized to WSi0.6N and the diffusion barrier capability was confirmed by physical analyses and electrical measurements. The electrical resistivity of the inlaid Cu was 1.9±0.1 µ Ωcm and contact resistivity between the first-level Cu and the second-level Cu was (1.54–5.78)×10-9 Ωcm2. The electromigration lifetime of laser-annealed Cu/WSiN wiring was found to be one order of magnitude longer than that of previously reported Cu interconnects. The activation energy for electromigration was determined to be 1.1 eV.

Interfacial energy calculation at interconnect‐metal/barrier‐metal interfaces for grain orientation control

The interfacial energy of interconnect‐metal/barrier‐metal interfaces in ultralarge‐scale integrations have been investigated numerically by assuming a simple additive interaction potential within a rigid‐lattice approximation. The calculation gave some noteworthy results: Al prefers the (111) orientation on a TiN(111) plane, but Cu did not have such a strong preference. Al(111) can be expected to show strong epitaxial growth on VNx(111), as did Cu on Nb(110). On the basis of the calculations, a Cu/Nb bilayered structure was sputter deposited sequentially by dc magnetron sputtering and examined for crystalline orientation by x‐ray‐diffraction analysis. Cu exhibited strong (111) orientation preference, and a narrow full width at half‐maximum in (111) rocking angle around the substrate normal.

Reliable High-k TiO2 Gate Insulator Formed by Ultrathin TiN Deposition and Low Temperature Oxidation

Phone/Fax : 045 -7 7 0-3663 / 3 57 7, E-mail : marsuo @ amc. toshiba.co j p l.Introduction As MOSFET gate lengths are scaled down to the 0.lpm regime or beyond, gate oxide thickness is desired to be thinned to below 3nm. High-K gate insulators are attractive materials, since physical thickness can be greater than that of SiO,, thereby preventing gate leakage current due to direct tunneling through ultrathin SiOr. Among the various high-K dielectrics, TiO, is reported to have a dielectric constant larger than 30, and therefore, physical thickness of TiO, can be 8 times larger than that of SiOr. According to the literature, TiO, is usually formed by TiO, CVD or reacrive sputtering Il] and the nliability of the film is not sufficient for gate dielectrics. On the other hand, Ti deposition and oxidation process result in slight interfacial reaction between Ti and the underlying layer such as Si, SiO2 or Si.NoIn this paper, a new TiQ formation method is prop-osed fbr ultrathin gate dielectrics. In this process, ultrathin TiN deposition and low temperature oxidation are used in order to avoid Si oxidation during TiO, formation and to improve the film quality of the TiO,.

Focus error reduction by photo-resist planarization in via-first dual damascene process

In order to reduce the focus error for the stacked mask process (SMAP) used in Cu/low-k dual damascene (DD) interconnect, a planarization technology of the under layer film by CMP was developed. Photo-resist was used for the under layer film. CMP slurry with resin abrasive was investigated for the photo-resist planarization. The slurry showed better planarity, lower risk to particle residue, and high selectivity to SiO/sub 2/ film. These advantages are attributable to the effects of the particle size and the material characteristics similar to photo-resist. Furthermore, it was found that it is effective for a higher CMP rate to turn the platen and head with lower rotational speed. Using the photo-resist planarization technology, application to via first DD process was investigated. It became clear that focus error reduction of 0.1 /spl mu/m is confirmed compared with conventional SMAP. The depth of focus (DOF) margin loss due to resist thickness variation caused by via density variation is completely canceled by photo-resist planarization.