Robert E. Busch

Bitline contacts in high density SRAMs: design for testability and stressability

Process scaling and the need for smaller SRAM cells challenges process technologies to make millions of robust and reliable bitline contacts on a single chip. Another challenge is to identify marginal, resistive and unreliable bitline contacts given the inherent electrical characteristics of the SRAM cell. This paper describes two design techniques that improve the screenability and stressability of bitline contacts in high-density SRAMs. These techniques are developed to overcome the lack of detectability of resistive bitline contacts in SRAM cells.

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns

A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for VDD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for VDD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock.