Romain Ritzenthaler

A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

The fringing fields induced by the drain and the source through the buried oxide (BOX) and substrate of short-channel silicon-on-insulator (SOI) MOSFETs cause a lowering of the threshold voltage. A physics-based model of the lateral coupling between the drain and the front channel is proposed. This simple 2-D model is based on conformal mapping and provides an accurate analytical description of the electrostatic potential in the BOX and particularly at the back interface (film BOX). The model includes the substrate-depletion effect. The main interest of the fringing field modeling is the optimization of the device dimensions and architecture (BOX thickness versus channel length, substrate doping, etc.) in sub-100-nm CMOS generations. This model can be used to evaluate the scalability of various architectures like fully depleted SOI, ground-plane MOSFET, double-gate MOSFET, and SOI on low-k BOX. It is also useful for the compact modeling of the body factor and the short-channel effects. The model is universal and naturally extends to the 3-D case of FinFET and triple-gate architectures. The coupling between the lateral gates through the BOX in narrow FinFET-like devices is shown to dominate the drain-to-body or the substrate-to-body coupling.

Plasma doping and reduced crystalline damage for conformally doped fin field effect transistors

Low frequency noise and hot carrier reliability analysis of the plasma doping scheme are investigated for advanced fin field effect transistor (FinFET) conformal doping. Plasma doping improves device performances and hot carrier reliability for both fin resistors and FinFETs due to the absence of crystalline damage for narrow fins. One decade lower noise level and Coulomb scattering coefficient related to the crystalline damage suppression are observed for the plasma doping compared to the standard ion-implantation.

Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-k dielectrics for nanoscale double-gate MOSFETs

Gate-leakage current reduction is the key motivation for the replacement of traditional SiO2 gate insulator with alternative gate dielectrics. In this work, a guideline for the determination of the suitable high-k candidate was reported in the case of a SiO2/high-k gate stack in a nanoscale double-gate (DG) MOSFET. Analytical models of direct tunneling gate leakage current with SiO2 as an interfacial layer have been considered. Using these models, the most promising high-k materials for different conditions were predicted, considering the effects of equivalent oxide thickness (EOT), gate leakage current, electron effective mass, dielectric constant-k value, barrier height and interfacial oxide thickness.

New Analysis Method for Time-Dependent Device-To-Device Variation Accounting for Within-Device Fluctuation

Variability of nanometer-size devices is a major challenge for circuit design. Apart from the as-fabricated variability, the postfabrication degradation introduces a time-dependent variability, originating from statistical distribution of charge location and number. The existing characterization techniques do not always capture the maximum degradation. Some of them does not separate the device-to-device variation from the charging fluctuation within the same device, either. The objective of this paper is to develop a new analysis method for characterizing time-dependent device-to-device variation, accounting for within-device fluctuation (TVF). The TVF captures the maximum degradation, separate device-to-device variation from within-device fluctuation, and reduce the data points by three orders of magnitude. It is shown that the popular data acquisition at discrete time points does not capture the fluctuation well and drain current must be measured continuously. The TVF shows that degradation has two components-a fluctuation with time and one whose discharge is not observed under a given bias. Although both of them increase with stress time, the correlation between them is weak, indicating two different origins.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Impact of the Substrate Orientation on CHC Reliability in n-FinFETs—Separation of the Various Contributions

In this paper, we perform a comparative analysis of the degradation induced by a channel hot carrier (CHC) in bulk n-FinFETs with rotated (100) and nonrotated (110) sidewall surfaces. CHC degradation includes several components, and separating each contribution is necessary for identifying different mechanisms in devices with different surface orientations. First, the permanent and recoverable components are separated based on the recovery phenomenon after the CHC stress, ascribed to the electron detrapping from the oxide bulk defects. Then, the contribution of generated interface states to the permanent component is quantified by charge pumping measurements. The nonrotated bulk FinFETs showed higher threshold voltage degradation at the maximum bulk current stress condition due to the higher interface precursor defect density compared with the rotated devices. On the other hand, the rotated bulk FinFETs showed higher threshold voltage degradation at the stress condition of VG = VD due to higher bulk defect trapping, ascribed to the lower physical oxide thickness.

1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor

The origin of performance difference between gate-first (GF) and replacement metal gate (RMG) fin field effect transistors (FinFETs) is investigated. Although RMG technology has the advantage of low thermal-budget, a 1.5 times lower effective hole mobility is shown for the high-k last (HKL) FinFET. Based on low frequency noise analysis, it is shown that the carrier transport is due to the carrier number fluctuation with correlated mobility fluctuation from the interface states. For HKL FinFETs, about 10 times higher trap density is observed compared to GF and high-k first FinFETs, which is generated during the dummy gate oxide removal process.

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (Vt, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

Self-heating on bulk FinFET from 14nm down to 7nm node

Self-heating effects in scaled bulk FinFETs from 14nm to 7nm node are discussed based on 3D FEM simulations and experimental measurements. Following a typical 0.7x scaling, heat confinement is expected to increase by 20% in Si-channel FinFETs and by another 57% for strained Ge-channel. Reducing the drive current needed to reach target performance by reducing capacitances, and fin depopulation help mitigate self-heating effects. These thermal behaviors propagates to AC circuit benchmark, resulting in ~5% performance variation for high performance devices due to device scaling and increased number of fins.

Development of a technique for characterizing bias temperature instability-induced device-to-device variation at SRAM-relevant conditions

SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-\(I\) -\(V\) , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias.