Steven Demuynck

AC NBTI studied in the 1 Hz -- 2 GHz range on dedicated on-chip CMOS circuits

We describe on-chip circuits specially designed and fabricated for the purpose of measuring the effect of AC NBTI on an individual, well-defined device in the wide frequency range on a single wafer. The circuits are designed to allow measurements in multiple modes, specifically, DC and AC NBTI (both interrupted and on-the-fly), on a single pFET and on a CMOS inverter, as well as charge-pumping characterization of the stressed pFET. The results indicate that AC NBTI is independent of the frequency in the 1 Hz-2 GHz range. The voltage and stress time acceleration is observed to be identical for both AC and DC NBTI stress

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

Impact of the barrier/dielectric interface quality on reliability of Cu porous-low-k interconnects

The purpose is to show that TDDB reliability of damascene structures has to be assessed as a system composed of a dielectric, copper diffusion barrier and copper. This becomes mandatory when porous low-k materials are considered, since barrier integrity is a key contributor in TDDB behavior. Solely addressing the dielectric properties is not adequate. When a not fully dense barrier is considered the apparent dielectric properties are degraded due to copper migration into the dielectric.

Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

Accurate determination of contact resistivities (P_c) below 1 × 10^-8 Ω · cm² is challenging. Among the frequently applied transmission line models (TLMs), circular TLM (CTLM) has a simple process flow, while refined TLM (RTLM) has a high Pc accuracy at the expense of a more complex fabrication. In this letter, we will present a novel model-multiring CTLM (MR-CTLM), which combines the advantages of a simple process and a high <i>Pc</i> extraction resolution. We fabricated ultralow<i>-Pc</i> Ti/n-Si contacts and demonstrated the capability of MR-CTLM to extract the P_c as low as 6.2 × 10^-9 Ω · cm² with high precision.

Reliability of MOL local interconnects

From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and overlay errors however challenge the integrity of the SiN dielectric between the gate and the local interconnects. In this work we study the reliability of this dielectric. It is found that the current between gate and the contacts is polarity independent and the breakdown voltage shows a strong polarity dependence. While within die good uniformity is observed, due to overlay errors the spacing between the gate and the contact varies across the wafer. This results in large VBD and tBD variability and for an intrinsic TDDB lifetime extrapolation correction for this non-uniformity required.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, and the worst case RC delay corner is 1.4X slower than best case corner. Our work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability. Consequently, a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend. It is shown that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can offer 30% smaller layout area than FinFET (or equivalent lateral 2D) based designs. Furthermore, we obtain a 19% reduction in routing area of a 32-bit multiplier implemented with a VFET-based standard-cell library w.r.t. the FinFET design.

A Comprehensive LER-Aware TDDB Lifetime Model for Advanced Cu Interconnects

A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived.

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO 2 /n-Si Contact

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height (qφb) MIS contact: Ti/TiO₂/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO₂/n-Si thermal stability study under different electron conduction mechanisms. We find that both qφ_b and contact resistivity (ρ_c) of the Ti/TiO₂/n-Si MIS contacts vary dramatically after mere 300°C-500°C 1-min rapid thermal treatments. The variations in qφ_b and ρ_c are related to the thermally driven TiO₂ decomposition. This thermal stability study of Ti/TiO₂/n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive lowwork function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed.

Cobalt bottom-up contact and via prefill enabling advanced logic and DRAM technologies

This work introduces two new metallization schemes using the electroless deposition (ELD) technique; one based on contact fill and one based on via prefill. One of the key features of the electroless process is its selective deposition, which can be used for bottom-up fill of high aspect ratio features. The feasibility of this Co ELD process is demonstrated on contacts landing on W and vias landing on Cu. Our simulation of the Co via resistance shows that it can serve as alternative to Cu with lower via resistance below 15nm dimension. The results from a planar capacitor study show that there is no degraded reliability in an organo-silicate glass low-k film when Co is in direct contact with this dielectric. Therefore, selective Co ELD process for contact and via prefill has the potential to enable future scaling of advanced logic and DRAM technologies.