Gen P. Lauer

STACKED PLANAR DOUBLE-GATE LAMELLAR FIELD-EFFECT TRANSISTOR

III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method

Low Temperature Salicide for Replacement Gate Nanowires

Structure and method to reduce shorting in STT-MRAM device

III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology

V-GROOVE SOURCE/DRAIN MOSFET AND PROCESS FOR FABRICATING SAME

Fin bipolar transistors having self-aligned collector and emitter regions

Structure and method to reduce shorting and process degradation in stt-mram devices

Magnetic tunnel junction with post-deposition hydrogenation

INTERNAL SPACER FORMATION FROM SELECTIVE OXIDATION FOR FIN-FIRST WIRE-LAST REPLACEMENT GATE-ALL-AROUND NANOWIRE FET