Jeffrey W. Sleight

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Measurement of Carrier Mobility in Silicon Nanowires

We report the first direct capacitance measurements of silicon nanowires (SiNWs) and the consequent determination of field carrier mobilities in undoped-channel SiNW field-effect transistors (FETs) at room temperature. We employ a two-FET method for accurate extraction of the intrinsic channel resistance and intrinsic channel capacitance of the SiNWs. The devices used in this study were fabricated using a top-down method to create SiNW FETs with up to 1000 wires in parallel for increasing the raw capacitance while maintaining excellent control on device dimensions and series resistance. We found that, compared with the universal mobility curves for bulk silicon, the electron and hole mobilities in nanowires are comparable to those of the surface orientation that offers a lower mobility.

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

We demonstrate the worlds first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFETs fabricated with gate-first high thermal budget processing with thin Tinv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFETs into CMOS devices yielded large SRAM arrays.

LOCOS-induced stress effects on thin-film SOI devices

LOCOS-induced stress effects on thin-film SOI devices are investigated. We show that as the field oxide thickness increases, degradation (enhancement) of nMOSFETs (pMOSFETs) I-V characteristics becomes increasingly pronounced. The total degradation or enhancement of I-V characteristics can reach /spl sim/40% of drive current for devices under certain processing conditions. Estimated stress results using four-point bending measurement show that the stress level on the silicon film is of order 1200 MPa for devices with /spl sim/40% of I-V degradation/enhancement. We attribute the stress phenomenon to the volumetric expansion of field oxide during the LOCOS process.

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs

Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that LEFF of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.

A continuous compact MOSFET model for fully- and partially-depleted SOI devices

A fully continuous compact SOI MOSFET model for circuit simulations, that automatically accounts for the for the correct body depletion condition, is presented. Unlike previously reported models that are derived for either fully-depleted (FD) or partially-depleted (PD) devices, our model accounts for the possible transitions between FD and PD behavior during the device operation.

Role of oxygen vacancies in V FB /V t stability of pFET metals on HfO 2

We demonstrate experimentally that the flatband/threshold voltages (V/sub FB//V/sub t/) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O/sub 2/ partial pressure during post-deposition N/sub 2//O/sub 2/ and/or forming gas annealing (FGA) with Re, Ru and Pt, the gate stack V/sub FB/ can change by as much as 750 mV. However, using Re as an example, it is shown that conditions can be optimized and V/sub FB//V/sub t/-tuning for pFETs can be achieved for aggressively scaled stacks. It is proposed that charge transfer from oxygen vacancies to the gate electrode, possible only for high workfunction metal gates, leads to the formation of a dipole layer near the gate which can shift V/sub FB//V/sub t/. The results indicate that V/sub FB//V/sub t/ control remains a formidable processing challenge with high workfunction metals on HfO/sub 2/.

Stress induced defects and transistor leakage for shallow trench isolated SOI

Anomalous leakage currents are observed for shallow trench isolated SOI transistors. The leakage effect is caused by stress induced dislocations in the device silicon islands. These dislocations are observed using cross-sectional TEM analysis. For the shallow trench isolation process employed, the leakage is most pronounced on SIMOX wafers when the buried oxide thickness is scaled down to 100 nm. Limiting fabrication stresses to a minimum is critical for eliminating this leakage defect and in obtaining a robust, high yielding SOI STI process.

High-Performance Undoped-Body 8-nm-Thin SOI Field-Effect Transistors

We have fabricated undoped-body short-channel extremely thin silicon-on-insulator (ETSOI) field-effect transistors (FETs) with 8-nm SOI thickness that exhibit the expected short-channel benefit compared with doped partially depleted SOI (PDSOI) FETs. Using a source/drain extension (SDE) last process with the SDE implants activated with diffusionless laser anneal, we demonstrate that the series resistance penalty can be minimized, which leads to ETSOI FET drive currents that are comparable to those of conventional thick-body PDSOI FETs.