Gen Tsutsui
IBM
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Publication
Featured researches published by Gen Tsutsui.
symposium on vlsi technology | 2014
Kang-ill Seo; Balasubramanian S. Haran; Dinesh Gupta; Dechao Guo; Theodorus E. Standaert; R. Xie; H. Shang; Emre Alptekin; D.I. Bae; Geum-Jong Bae; C. Boye; H. Cai; D. Chanemougame; R. Chao; Kangguo Cheng; Jin Cho; K. Choi; B. Hamieh; J. Hong; Terence B. Hook; L. Jang; J. E. Jung; R. Jung; Duck-Hyung Lee; B. Lherron; R. Kambhampati; Bum-Suk Kim; H. Kim; Kyu-Sik Kim; T. S. Kim
A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.
international electron devices meeting | 2013
Qing Liu; M. Vinet; J. Gimbert; Nicolas Loubet; Romain Wacquez; L. Grenouillet; Y. Le Tiec; Ali Khakifirooz; T. Nagumo; Kangguo Cheng; H. Kothari; D. Chanemougame; F. Chafik; S. Guillaumet; J. Kuss; F. Allibert; Gen Tsutsui; J. Li; Pierre Morin; Sanjay Mehta; Richard Johnson; Lisa F. Edge; Shom Ponoth; T. Levin; Sivananda K. Kanakasabapathy; Balasubramanian S. Haran; Huiming Bu; J.-L Bataillon; O. Weber; O. Faynot
We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (L<sub>G</sub>) of 20nm and BOX thickness (T<sub>BOX</sub>) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (I<sub>eff</sub>) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (I<sub>off</sub>) of 100nA/μm and V<sub>dd</sub> of 0.9V. Excellent electrostatics is obtained, demonstrating the scalability of these devices to14nm and beyond. Very low A<sub>Vt</sub> (1.3mV·μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.
ieee soi 3d subthreshold microelectronics technology unified conference | 2014
Terence B. Hook; F. Allibert; Karthik Balakrishnan; Bruce B. Doris; Dechao Guo; Narasimha R. Mavilla; Edward J. Nowak; Gen Tsutsui; Richard G. Southwick; Jay W. Strane; Xin Sun
FinFETs may in principle be built on either bulk [1-3] or SOI [4-5] substrates. In this paper we will review some of the technical issues associated with choice of substrate, directly comparing empirical results on 10nm hardware for which all the other processes are as much the same as possible. Furthermore, we will discuss the challenges beyond the 10nm generation, where fundamental changes in materials may render the debate moot. Our conclusion and prognosis is that SOI was, is, and will continue to be the technically superior choice.
symposium on vlsi technology | 2016
Praneet Adusumilli; Emre Alptekin; Mark Raymond; Nicolas L. Breil; F. Chafik; Christian Lavoie; D. Ferrer; S. Jain; V. Kamineni; Ahmet S. Ozcan; S. Allen; J. J. An; V. S. Basker; R. Bolam; Huiming Bu; Jin Cai; J. Demarest; Bruce B. Doris; E. Engbrecht; S. Fan; J. Fronheiser; Oleg Gluschenkov; Dechao Guo; B. Haran; D. Hilscher; Hemanth Jagannathan; D. Kang; Y. Ke; J. Kim; Siyuranga O. Koswatta
We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.
symposium on vlsi technology | 2016
Dechao Guo; Gauri Karve; Gen Tsutsui; K-Y Lim; Robert R. Robison; Terence B. Hook; R. Vega; Duixian Liu; S. Bedell; Shogo Mochizuki; Fee Li Lie; Kerem Akarvardar; M. Wang; Ruqiang Bao; S. Burns; V. Chan; Kangguo Cheng; J. Demarest; Jody A. Fronheiser; Pouya Hashemi; J. Kelly; J. Li; Nicolas Loubet; Pietro Montanini; B. Sahu; Muthumanickam Sankarapandian; S. Sieg; John R. Sporre; J. Strane; Richard G. Southwick
SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.
ieee soi 3d subthreshold microelectronics technology unified conference | 2013
Ali Khakifirooz; R. Sreenivasan; B. N. Taber; F. Allibert; Pouya Hashemi; W. Chern; N. Xu; E. C. Wall; S. Mochizuki; J. Li; Y. Yin; Nicolas Loubet; S. M. Mignot; Darsen D. Lu; H. He; Tenko Yamashita; Pierre Morin; Gen Tsutsui; C-Y Chen; V. S. Basker; Theodorus E. Standaert; Kangguo Cheng; T. Levin; Bich-Yen Nguyen; T-S King Liu; Dechao Guo; Huiming Bu; Kern Rim; Bruce B. Doris
Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained semiconductor, e.g. in the form of strained silicon directly on insulator (SSDOI) or strained SiGe-on-insulator has the advantage that the strain is independent of the device pitch or gate length as long as the active region is made sufficiently long and the strain is maintained throughout the device processing. We have already shown that in a FinFET structure the starting biaxial strain in the SSDOI substrate is converted to a more beneficial uniaxial strain, strain can be maintained throughout typical thermal processing, and demonstrated roughly 15% increase in NFET performance in deeply scaled FinFETs. However, this is still far less than the performance gain we reported recently in ETSOI devices. In this work, for the first time we report NFET performance gain in SSDOI FinFETs fabricated with contacted gate pitch (CGP) down to 64nm.
symposium on vlsi technology | 2017
Gen Tsutsui; Huimei Zhou; Andrew M. Greene; Robert R. Robison; Jie Yang; Juntao Li; Christopher Prindle; John R. Sporre; Eric R. Miller; Derrick Liu; Ryan Sporer; Bob Mulfinger; Tim McArdle; Jin Cho; Gauri Karve; Fee Li Lie; Siva Kanakasabapathy; Rick Carter; Dinesh Gupta; Andreas Knorr; Dechao Guo; Huiming Bu
SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.
international electron devices meeting | 2016
Gen Tsutsui; Ruqiang Bao; Kwan-yong Lim; Robert R. Robison; Reinaldo A. Vega; Jie Yang; Zuoguang Liu; Miaomiao Wang; Oleg Gluschenkov; Chun Wing Yeung; Koji Watanabe; Steven Bentley; Hiroaki Niimi; Derrick Liu; Huimei Zhou; Shariq Siddiqui; Hoon Kim; Rohit Galatage; Rajasekhar Venigalla; Mark Raymond; Praneet Adusumilli; Shogo Mochizuki; Thamarai S. Devarajan; Bruce Miao; B. Liu; Andrew M. Greene; Jeffrey Shearer; Pietro Montanini; Jay W. Strane; Christopher Prindle
Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.
ieee international conference on solid state and integrated circuit technology | 2014
Dechao Guo; H. Shang; Kang-ill Seo; Balasubramanian S. Haran; Theodorus E. Standaert; Dinesh Gupta; Emre Alptekin; D.I. Bae; Geum-Jong Bae; D. Chanemougame; Kangguo Cheng; Jin Cho; B. Hamieh; J. Hong; Terence B. Hook; J. E. Jung; R. Kambhampati; Bum-Suk Kim; H. Kim; Kyu-Sik Kim; T. S. Kim; Duixian Liu; H. Mallela; P. Montanini; M. Mottura; S. Nam; I. Ok; Youn-sik Park; A. Paul; Christopher Prindle
In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.
ieee soi 3d subthreshold microelectronics technology unified conference | 2013
Abhijeet Paul; Chun-Chen Yeh; Theodorus E. Standaert; Jeffrey B. Johnson; Andres Bryant; Neeraj Tripathi; Gen Tsutsui; Tenko Yamashita; Veeraraghvan S. Basker; Johnathan E. Faltermeier; Jin Cho; Huiming Bu; M. Khare
This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.