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Dive into the research topics where Huiming Bu is active.

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Featured researches published by Huiming Bu.


international electron devices meeting | 2009

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

Kangguo Cheng; Ali Khakifirooz; Pranita Kulkarni; Shom Ponoth; J. Kuss; Davood Shahrjerdi; Lisa F. Edge; A. Kimball; Sivananda K. Kanakasabapathy; K. Xiu; Stefan Schmitz; Thomas N. Adam; Hong He; Nicolas Loubet; Steven J. Holmes; Sanjay Mehta; D. Yang; A. Upham; Soon-Cheon Seo; J. L. Herman; Richard Johnson; Yu Zhu; P. Jamison; B. Haran; Zhengmao Zhu; L. H. Vanamurth; S. Fan; D. Horak; Huiming Bu; Philip J. Oldiges

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at Ioff = 300 pA/µm, VDD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.


international electron devices meeting | 2011

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Siddarth A. Krishnan; Unoh Kwon; Naim Moumen; M.W. Stoker; Eric C. Harley; Stephen W. Bedell; D. Nair; Brian J. Greene; William K. Henson; M. Chowdhury; D.P. Prakash; Ernest Y. Wu; Dimitris P. Ioannou; E. Cartier; Myung-Hee Na; Seiji Inumiya; Kevin McStay; Lisa F. Edge; Ryosuke Iijima; J. Cai; Martin M. Frank; M. Hargrove; Dechao Guo; A. Kerber; Hemanth Jagannathan; Takashi Ando; Joseph F. Shepard; Shahab Siddiqui; Min Dai; Huiming Bu

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.


international electron devices meeting | 2009

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Hirohisa Kawasaki; Veeraraghavan S. Basker; Tenko Yamashita; Chung Hsun Lin; Yu Zhu; J. Faltermeier; Stefan Schmitz; J. Cummings; Sivananda K. Kanakasabapathy; H. Adhikari; Hemanth Jagannathan; Arvind Kumar; K. Maitra; Junli Wang; Chun-Chen Yeh; Chao Wang; Marwan H. Khater; M. Guillorn; Nicholas C. M. Fuller; Josephine B. Chang; Leland Chang; R. Muralidhar; Atsushi Yagishita; R. Miller; Q. Ouyang; Y. Zhang; Vamsi Paruchuri; Huiming Bu; Bruce B. Doris; Mariko Takayanagi

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.


symposium on vlsi technology | 2010

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Veeraraghavan S. Basker; Theodorus E. Standaert; Hirohisa Kawasaki; Chun-Chen Yeh; Kingsuk Maitra; Tenko Yamashita; Johnathan E. Faltermeier; H. Adhikari; Hemanth Jagannathan; Junli Wang; H. Sunamura; Sivananda K. Kanakasabapathy; Stefan Schmitz; J. Cummings; A. Inada; Chung-Hsun Lin; Pranita Kulkarni; Yu Zhu; J. Kuss; T. Yamamoto; Arvind Kumar; J. Wahl; Atsushi Yagishita; Lisa F. Edge; R. H. Kim; E. Mclellan; Steven J. Holmes; R. C. Johnson; T. Levin; J. Demarest

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.


symposium on vlsi technology | 2007

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Michael P. Chudzik; Bruce B. Doris; Renee T. Mo; Jeffrey W. Sleight; E. Cartier; C. Dewan; Dae-Gyu Park; Huiming Bu; W. Natzle; W. Yan; C. Ouyang; K. Henson; Diane C. Boyd; S. Callegari; R. Carter; D. Casarotto; Michael A. Gribelyuk; M. Hargrove; W. He; Young-Hee Kim; Barry P. Linder; Naim Moumen; Vamsi Paruchuri; J. Stathis; M. Steen; A. Vayshenker; X. Wang; Sufi Zafar; Takashi Ando; Ryosuke Iijima

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFETs fabricated with gate-first high thermal budget processing with thin Tinv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFETs into CMOS devices yielded large SRAM arrays.


symposium on vlsi technology | 2010

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

Qing Liu; Atsushi Yagishita; Nicolas Loubet; Ali Khakifirooz; Pranita Kulkarni; Toyoji Yamamoto; Kangguo Cheng; M. Fujiwara; J. Cai; D. Dorman; Sanjay Mehta; Prasanna Khare; K. Yako; Yu Zhu; S. Mignot; Sivananda K. Kanakasabapathy; S. Monfray; F. Boeuf; Charles W. Koburger; H. Sunamura; Shom Ponoth; Balasubramanian S. Haran; A. Upham; Richard Johnson; Lisa F. Edge; J. Kuss; T. Levin; N. Berliner; Effendi Leobandung; T. Skotnicki

We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V<inf>bb</inf>) enables V<inf>t</inf> modulation of more than 125mV with a V<inf>bb</inf> of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V<inf>t</inf> and power management applications. We explore the impact of GP, BOX thickness and V<inf>bb</inf> on local V<inf>t</inf> variability for the first time. Excellent A<inf>Vt</inf> of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I<inf>g</inf>) and lower external resistance (R<inf>ext</inf>), thanks to a thicker inversion gate dielectric (T<inf>inv</inf>) and body (T<inf>si</inf>) thickness.


symposium on vlsi technology | 2014

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kang-ill Seo; Balasubramanian S. Haran; Dinesh Gupta; Dechao Guo; Theodorus E. Standaert; R. Xie; H. Shang; Emre Alptekin; D.I. Bae; Geum-Jong Bae; C. Boye; H. Cai; D. Chanemougame; R. Chao; Kangguo Cheng; Jin Cho; K. Choi; B. Hamieh; J. Hong; Terence B. Hook; L. Jang; J. E. Jung; R. Jung; Duck-Hyung Lee; B. Lherron; R. Kambhampati; Bum-Suk Kim; H. Kim; Kyu-Sik Kim; T. S. Kim

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.


IEEE Electron Device Letters | 2011

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High-

Kingsuk Maitra; Ali Khakifirooz; Pranita Kulkarni; Veeraraghavan S. Basker; Jonathan Faltermeier; Hemanth Jagannathan; Hemant Adhikari; Chun-Chen Yeh; Nancy Klymko; Katherine L. Saenger; Theodorus E. Standaert; Robert J. Miller; Bruce B. Doris; Vamsi Paruchuri; Dale McHerron; James O'Neil; Effendi Leobundung; Huiming Bu

Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e.,<i>L</i><sub>GATE</sub> ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-first flow. A “long and narrow” fin layout (i.e., fin length ~ 1 μm) was leveraged to preserve uniaxial tensile strain in the transistors. These devices exhibit drive currents suitable for high-performance logic technology. The change in the slope of <i>R</i><sub>ON</sub> - <i>L</i><sub>GATE</sub> (dR<sub>ON</sub>/dL<sub>GATE</sub>), transconductance <i>G</i><sub>MSAT</sub>, and injection velocity (<i>v</i><sub>inj</sub>) measurements indicate a ~ 15% mobility-induced <i>I</i><sub>ON</sub> enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths. Raman measurements conducted on SSOI substrates after fin formation demonstrate the preservation of ~ 1.3-GPa uniaxial tensile strain even after 1100°C annealing.


international solid-state circuits conference | 2010

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Ali Khakifirooz; Kangguo Cheng; Basanth Jagannathan; Pranita Kulkarni; Jeffrey W. Sleight; Davood Shahrjerdi; Josephine B. Chang; Sungjae Lee; Junjun Li; Huiming Bu; Robert J. Gauthier; Bruce B. Doris; Ghavam G. Shahidi

Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1–5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.


international soi conference | 2010

/Metal-Gate nFinFETs for High-Performance Logic Applications

Kangguo Cheng; Ali Khakifirooz; Pranita Kulkarni; Shom Ponoth; J. Kuss; Lisa F. Edge; A. Kimball; Sivananda K. Kanakasabapathy; Stefan Schmitz; Thomas N. Adam; Hong He; Sanjay Mehta; A. Upham; Soon-Cheon Seo; J. L. Herman; Richard Johnson; Yu Zhu; P. Jamison; Balasubramanian S. Haran; Zhengmao Zhu; S. Fan; Huiming Bu; Devendra K. Sadana; P. Kozlowski; J. O'Neill; Bruce B. Doris; Ghavam G. Shahidi

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

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