Robert R. Robison

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier mobility in both PMOS and NMOS FETs is presented for the first time. A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability.

Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs

Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective drain-current enhancement over coprocessed symmetric control devices is 10%. Analysis reveals that the dominant physical mechanism, which accounts for two-third of the total enhanced drain current, is an 8% increase in the source-side injection velocity. The remaining one-third is attributed to the decreased drain-induced barrier lowering. This paper concludes with an analysis of the switching characteristics of CMOS inverters composed of an asymmetric NFET and a companion symmetric PFET and shows a 5% improvement in the delay. The improvement is explained in terms of the increased velocity and 30% reduction in drain junction capacitance.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

SiGe FinFET for practical logic libraries by mitigating local layout effect

SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

2 nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond

In this paper we report on a comprehensive study of Silicon-Germanium channel (cSiGe) physics, layout effects and impact on device performance. This work demonstrates a 2nd generation of dual channel technology, which meets the 22nm high performance technology (HP) requirement. Modeling and simulation are used to optimize the process to obtain a 10% Short Channel Effect (SCE) improvement and an overall 20% performance enhancement. This 2nd generation high performance dual channel process has been integrated into a manufacturable and yieldable technology, thereby providing a solid platform for introduction of SiGe FinFet technology.

Density scaling beyond the FinFET: Architecture considerations for gate-all-around CMOS

The promise of improved electrostatics and the ability to increase the amount of effective width (Weff) available in a given device footprint drove the semiconductor industry from planar CMOS transistors to the FinFET transistor starting at the 22 nm node. Numerous manufacturers are in large-scale production of 16 and 14 nm node FinFET technologies and there is no indication that a change in device architecture is planned for the 10 or 7 nm nodes. Looking beyond 7 nm, the scaling challenges of the FinFET are expected to increase dramatically. In particular, continued scaling of the fin width and fin pitch may reach a physical limit due to a combination of quantum effects, patterning process realities and contact architecture limitations. It is well known that gate-all-around (GAA) devices demonstrate improved electrostatics over double or triple-gated FinFET devices. In view of the impending difficulties occasioned by FinFET scaling, it is necessary to take a critical look at the possibility of a GAA CMOS device technology. In this paper, I will explore this topic by presenting relevant TCAD and experimental work on single and stacked GAA devices. The TCAD illustrates that a properly designed stacked GAA device architecture can show superior performance over a scaled FinFET reference. I will conclude by presenting experimental work to substantiate this claim.