Geordie Braceras

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-power CMOS Technology. The 62-mm2 die features read-assist and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms. Hardware measurements demonstrate the fail-count improvements achieved by integrating these techniques. The decrease in fail-count provides a 100-mV improvement of VDDMIN during the read operation. Write operations are also improved, especially with weak NFET cell transistors. The circuit techniques have been replicated on a 72-Mb stand-alone standard SRAM product where the area overhead from the additional circuits is approximately 4%. The 32-Mb SRAM has also been successfully migrated to other yield-learning SRAMs in 45-nm bulk and SOI technologies with minimum circuit changes

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology [1]. Figure 14.1.1 shows the 0.154μm2 bitcell (BC). A 2× size reduction from the previous 45nm design [2] is enabled by an equal 2× reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDDMIN operation is enabled by three assist features. Stability is improved by a bitline (BL) regulation scheme. Enhancements to the write path include an increase of 40% of BL boost voltage. Finally, a BC-tracking delay circuit improves both performance and yield across the process space.

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management

A 450 ps access-time 512 Kb SRAM macro is fabricated in a 45 nm SOI technology. The macro is adapted for use as the principal growable embedded-SRAM block in a 45 nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 58% reduction in read power consumption under constant voltage and frequency compared to the previous generation macro. Also described is a single-device dynamic-leakage-suppression scheme that reduces total leakage power consumption by 37% with no wake-up-cycle requirements.

A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 /spl mu/m CMOS process

A 35OMHz 4Mb SRAM chip in 2.5V 0.3/spl mu/m CMOS achieves a 4.1 ns flow-through access and uses self-timed, self-resetting, and low-signal swing circuits. The SRAM interfaces to LVTTL levels with a PECL clock, or to HSTL levels with either a single-ended or differential clock. The chip can be packaged in either 128k/spl times/36 or 256k/spl times/18 organizations and supports pipeline, dual-clock flowthrough, or register-latch timing protocols. A voltage regulator drives the internal power grid. High-speed circuits are used for the critical read performance path, and low-power static circuits are used in paths that do not gate chip performance.

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

This paper describes an 8 Mb SRAM test chip that has been designed and fabricated in a 45 nm Silicon-On-Insulator (SOI) CMOS technology. The test chip comprises of sixteen 512 kb instances and is designed for use as the principal compilable one-port embedded-SRAM block in a 45 nm ASIC library. Challenges associated with SRAM cell design in SOI are overcome and resulted in a cell size of 0.315 mum2 . The paper introduces two circuit techniques that address the AC and DC power consumption issues facing todays embedded-SRAMs. The first technique addresses AC power dissipation by utilizing a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 68% improvement in read power under constant voltage and frequency compared to the previous generation macro . The second technique addresses the DC power consumption by introducing a single-device, header based dynamic leakage suppression scheme that reduces total macro leakage power by 38% with no wake-up cycle requirements.

A 940 MHz data rate 8 Mb CMOS SRAM

An 8 Mb CMOS SRAM cycles at 470 MHz and provides a data rate of 940 MHz when run in the double-data rate (DDR) mode. Improved redundancy minimizes SRAM latency, enabling 3.4 ns access time. The HSTL I/O performance is enhanced by using flip-chip C4 packaging and by decoupling the I/O supply on-chip. The 8 Mb SRAM has an architecture to allow both /spl times/18 and /spl times/36 organizations, as well as a 4 Mb cut-down.

A 200 MHz internal/66 MHz external 64 kB embedded virtual three-port cache SRAM

A 66 MHz, 64 kB three-port cache SRAM has a 95 /spl mu/m/sup 2/ six-device cell and three internal pipelined accesses, allowing the single-port SRAM array to operate as a true multiported RAM. Using 0.8 /spl mu/m CMOS technology (Leff=0.45 /spl mu/m), the self-timed memory employs pipelined circuit techniques to independently access the array three times for every 15 ns processor cycle, two read/write processor accesses and one write-only memory access. The RAM is organized as 4 k/spl times/36/spl times/4 for processor interface, 2 k/spl times/288 for read memory port or storeback buffer (SBB), and 8 k/spl times/72 memory-write interface (reload buffer). Other features include cache line zeroing, four-way set associativity, byte-write controllability, port prioritization, address compare by-pass, array built-in self-test (ABIST), and byte alignment for misaligned memory accesses.<<ETX>>