John A. Gabric

Design considerations for MRAM

MRAM (magnetic random access memory) technology, based on the use of magnetic tunnel junctions (MTJs) as memory elements, is a potentially fast nonvolatile memory technology with very high write endurance. This paper is an overview of MRAM design considerations. Topics covered include MRAM fundamentals, array architecture, several associated design studies, and scaling challenges. In addition, a 16-Mb MRAM demonstration vehicle is described, and performance results are presented.

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology [1]. Figure 14.1.1 shows the 0.154μm2 bitcell (BC). A 2× size reduction from the previous 45nm design [2] is enabled by an equal 2× reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDDMIN operation is enabled by three assist features. Stability is improved by a bitline (BL) regulation scheme. Enhancements to the write path include an increase of 40% of BL boost voltage. Finally, a BC-tracking delay circuit improves both performance and yield across the process space.

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management

A 450 ps access-time 512 Kb SRAM macro is fabricated in a 45 nm SOI technology. The macro is adapted for use as the principal growable embedded-SRAM block in a 45 nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 58% reduction in read power consumption under constant voltage and frequency compared to the previous generation macro. Also described is a single-device dynamic-leakage-suppression scheme that reduces total leakage power consumption by 37% with no wake-up-cycle requirements.

An 11-ns 8K*18 CMOS static RAM with 0.5- mu m devices

An experimental 11-ns 8 K*18 static RAM fabricated in a 1.2- mu m CMOS technology with 0.5- mu m channel lengths is described. Novel interface circuits allow full TTL-level compatibility with a scaled 3.6-V V/sub dd/. Synchronous clocking and automatic restore operations were implemented to realize high-speed access and a fast cycle data rate of 8 ns. Double-word-line architecture and a pulsed word-line technique reduce power dissipation. Other features include on-chip test circuitry that increases tester timing accuracy and word-line redundancy. The design uses a single-poly, double-metal technology with a CMOS six-transistor cell of 235 mu m/sup 2/ to yield a chip size of 60 mm/sup 2/. >

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

This paper describes an 8 Mb SRAM test chip that has been designed and fabricated in a 45 nm Silicon-On-Insulator (SOI) CMOS technology. The test chip comprises of sixteen 512 kb instances and is designed for use as the principal compilable one-port embedded-SRAM block in a 45 nm ASIC library. Challenges associated with SRAM cell design in SOI are overcome and resulted in a cell size of 0.315 mum2 . The paper introduces two circuit techniques that address the AC and DC power consumption issues facing todays embedded-SRAMs. The first technique addresses AC power dissipation by utilizing a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 68% improvement in read power under constant voltage and frequency compared to the previous generation macro . The second technique addresses the DC power consumption by introducing a single-device, header based dynamic leakage suppression scheme that reduces total macro leakage power by 38% with no wake-up cycle requirements.