Fred J. Towler

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-power CMOS Technology. The 62-mm2 die features read-assist and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms. Hardware measurements demonstrate the fail-count improvements achieved by integrating these techniques. The decrease in fail-count provides a 100-mV improvement of VDDMIN during the read operation. Write operations are also improved, especially with weak NFET cell transistors. The circuit techniques have been replicated on a 72-Mb stand-alone standard SRAM product where the area overhead from the additional circuits is approximately 4%. The 32-Mb SRAM has also been successfully migrated to other yield-learning SRAMs in 45-nm bulk and SOI technologies with minimum circuit changes

An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms

A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process

A 300 MHz, 1 Mb SRAM with 5.4 ns access in 3.3 V, 0.5 /spl mu/m CMOS uses self-timed and self-resetting circuits. A dual-clock, flow-through read protocol optimizes data window control and a 750 ps setup-and-hold window for all input signals is achieved through floorplanning, receiver design and localized input-signal registering. The SRAM interfaces with high-speed transceiver logic (HSTL) levels through high-speed, noise-tolerant receivers. Programmable impedance output drivers for HSTL interfaces match transmission line impedance to within 10% tolerances over process, voltage and temperature variations.

A 128Kb CMOS static random-access memory

This paper describes an all-CMOS 128Kb static random-access memory (SRAM) with emitter-coupled-logic (ECL) I/O compatibility which was designed for the air-cooled Enterprise System/9000™ processors. Access time of 6.5 ns is achieved using 0.5-µm channel length and 1.0-µm minimum geometry. Pipelining and self-resetting circuit techniques permit the chip to operate with cycle time less than access time. To achieve the high-reliability requirement in the TCM environment, a novel technique utilizing a sacrificial substrate is used to “burn in” chips prior to their attachment to the TCM.

Deep trench capacitor in three dimensional through silicon via keepout area for electrostatic discharge protection

To fully enable and leverage the power of advanced processors, products must have abundant cache memory with much shorter access paths without increasing chip size. This requires growing products in the z-direction by building stacked chips (3D chips). To optimize 3D product costs, the area consumed by other processing requirements such as electrostatic discharge (ESD) protection needs to be as efficient as possible. Placing ESD structures made with deep trench capacitors in three dimensional Through silicon via keepout areas optimizes silicon area since these structures enable placement of ESD devices in space that would otherwise not be used.

Parametric composite limited yield index for functional circuits yield prediction

In this paper we present an early detection mechanism for semiconductor circuit yield prediction and tracking. Several discrete devices used as components of functional circuits have been examined by their first-metal level test data and correlated to the higher metal level functional yield. A concept of Device Health Composite Yield is also introduced in this paper.

A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing (of SRAMs)

A design is presented using a multilayered ceramic (MLC) substrate as the basis for the wafer-tester interface. A 27*27 matrix of pads on 225 mu m centers is contacted; this design replaces a hand-wire interface between the wafer probe and tester performance board. Significant reductions in signal crosstalk and power supply noise are realized.<<ETX>>