George Bryce

A new complementary hetero-junction vertical Tunnel-FET integration scheme

This paper presents a new integration scheme for complementary hetero-junction vertical Tunnel FETs (VTFETs), whereby a sacrificial source layer is used during the device fabrication and replaced by the final hetero-source materials, respectively for n- or p-TFETs, thereby minimizing the thermal budget applied to the source junctions. With the demonstration of this source-replacement-last module for a vertical Ge hetero-junction n-TFET, we show that it is possible to grow highly doped hetero-junctions on a Si channel with steep doping profiles and without damaging the high-κ gate-dielectric interface. This scheme allows for the integration of complementary low-bandgap materials on a Si platform providing high on-currents combined with the Si channel based low off-currents.

Highly reliable CMOS-integrated 11MPixel SiGe-based micro-mirror arrays for high-end industrial applications

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.

Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme

The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approach, whereby a dummy source is replaced at the end of the process flow by the final source material to form an heterojunction. We show that the source can be successfully replaced while maintaining the gate dielectric integrity in the gate-source overlap (GS-OL) region and selectively to the exposed materials. Due to the in situ-doped epitaxial-grown source and the low thermal budget, this integration scheme leads to the formation of a highly doped source and an abrupt tunnel heterojunction and allows the integration of complementary devices. Electrical characterization of the devices shows performance improvement over their SiGe-source heterojunction and Si homojunction vertical TFET counterparts. Temperature dependence indicates that the subthreshold region of the devices is degraded due to trap-assisted tunneling (TAT). Band-to-band tunneling (BTBT) contribution is, however, revealed at low temperature (78 K) with a minimum point slope of ~50 mV/decade. The impact on performance of different device parameters is assessed. The amount of GS-OL or crystalline Ge (c-Ge) thickness in the source does not affect the device characteristics owing to the fact that the devices are dominated by point tunneling. On the other hand, the thickness of the gate dielectric as well as the doping profile at the tunnel junction modifies the device performance. The gate-drain underlap is shown to reduce the ambipolar behavior of the devices without affecting their ON-characteristics. Very low variability is measured for the ON-current in the devices where BTBT dominates, while variability increases in the TAT region.

Simultaneous Optimization of the Material Properties, Uniformity and Deposition Rate of Polycrystalline CVD and PECVD Silicon-Germanium Layers for MEMS Applications

The deposition rate is significantly enhanced by utilizing a plasma-enhanced chemical vapor deposition (PECVD) method. This method produces however an amorphous SiGe deposition. To induce crystallization in the bulk PECVD layer it has to be deposited on top of a chemical vapor deposited (CVD) SiGe layer [4] which in itself is deposited on top of a thin PECVD seed layer (see Fig 1). The purpose of the PECVD seed layer is to minimize the incubation time. The CVD and PECVD depositions are performed sequentially in an Applied Materials Centura CxZ chamber.

SiGe MEMS technology: a platform technology enabling different demonstrators

In imecs 200mm fab a dedicated poly-SiGe above-IC MEMS (Micro Electro-Mechanical Systems) platform has been set up to integrate MEMS and its readout and driving electronics on one chip. In the Flemish project Gemini the possibilities of this platform have been further explored together with the project partners. Three different demonstrators were realized: mirrors for display applications, grating light valves (GLV) and accelerometers. Whereas the mirrors and GLVs are made with a similar to 300 nm thick SiGe structural layer plus optical coating, the SiGe structural layer thickness for the accelerometers is 4 mu m in order to improve the capacitive readout of in-plane devices. The processing and measurement results of these functional demonstrators are shown in this paper. These new demonstrators reconfirm the generic nature of the SiGe MEMS platform.

Improvement of PECVD Silicon–Germanium Crystallization for CMOS Compatible MEMS Applications

This paper investigates the influence of the electrode spacing, chamber pressure, total gas flow, and H 2 dilution on the crystallinity, resistivity, uniformity, and stress of polycrystalline silicon-germanium (poly-SiGe) films grown by plasma-enhanced chemical vapor deposition (PECVD). Boron-doped PECVD SiGe films of 1.6 μm thick are deposited on 400 nm chemical vapor deposition layers from SiH 4 , GeH 4 , and B 2 H 6 precursors. The microstructure is verified by transmission electron microscopy and by X-ray diffraction. It was discovered that for constant temperature and deposition rate, the PECVD SiGe microstructure changes from completely amorphous to polycrystalline by increasing the electrode spacing and pressure due to reduced ion bombardment. A process window of an electrode spacing and pressure for the PECVD poly-SiGe deposition is thus identified based on a sheet resistance mapping method. Increasing the total gas flow dramatically improves the within-wafer crystallinity variation and further reduces the resistivity. Increasing the H 2 flow during PECVD shifts the stress from -51 to 17 MPa and further reduces the crystallinity variation over the wafer. In addition, the effect of changing the SiH 4 to GeH 4 ratio and the in situ boron doping by adding B 2 H 6 is also investigated. The findings in this paper are expected to facilitate the use of poly-SiGe in the above complementary metal oxide semiconductor (CMOS) microelectromechanical system (MEMS) applications.

Development, Optimization and Evaluation of a CF4 Pretreatment Process to Remove Unwanted Interfacial Layers in Stacks of CVD and PECVD Polycrystalline Silicon-Germanium for MEMS Applications

Due to the requirements of low deposition temperatures (≤ 460 °C) and thicknesses of up to 10 μm for MEMS applications, the deposition rate must be enhanced by utilizing a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. This method typically produces however an amorphous SiGe deposition at 460 °C or below [4]. One method of inducing polycrystallization in the bulk PECVD layer is to deposit it on top of a thin (~400 nm) polycrystalline CVD (Chemical Vapor Deposition) SiGe seed layer [5]. In this way the polycrystallinity of the CVD SiGe seed layer is transferred into the PECVD SiGe layers. This effect is illustrated in Figure 1 (bottom PECVD layer).

Wafer bow of substrate transfer process for GaNLED on Si 8 inch

This paper investigates the wafer bow induced during the substrate transfer process for GaN LED on Si (111) 8 inch wafers. The substrate transfer process is to transfer the thin GaN LED device layer to a carrier wafer using a CuSnCu permanent bonding layer. The process generates tensile bow on a wafer due to the high tensile stress of the Cu or the CuxSny intermetallic layer after bonding. Understanding the wafer bow evolution during the substrate transfer is very important to get a good control of the process. The high wafer bow value may cause problems for some automatic handling tools in the production line or affect process quality such as in lithography. The influence of substrate thickness and Cu metallization thickness on the wafer bow has been studied. A bow compensation layer can be used to compensate the tensile bow, thus minimizing the wafer bow after the substrate transfer process.

Novel miniaturized packaging for implantable electronic devices

A novel biocompatible packaging process for implantable electronic systems is described, combining excellent biocompatibility and hermeticity with extreme miniaturization. Biocompatible and clean room compatible materials and integration processes are evaluated and selected for die encapsulation and interconnection. Cytotoxicity, diffusion tests and corrosion tests using DI water and more aggressive bio-fluids demonstrated promising performance of the packaging.