Gert Claes

Above-IC generic poly-SiGe thin film wafer level packaging and MEM device technology: Application to accelerometers

We present an attractive poly-SiGe thin film packaging and MEM (Micro Electro-Mechanical) platform technology for integrating various packaged MEM devices above standard CMOS. The packages, having cavities as large as 1mm2, make use of pillars designed to withstand subsequent molding during 1st level packaging. Covers on top of the release holes avoid deposition inside the cavity during sealing. Hermeticity is proven in vacuum, air and N2 atmosphere and at different temperatures. Packaged functional accelerometers sealed at a pressure around 1bar, have an equivalent performance in measuring accelerations of about 1g compared to a piezoelectric commercial reference device.

Poly-SiGe-Based MEMS Thin-Film Encapsulation

This paper presents an attractive poly-SiGe thin-film packaging and MEM (microelectromechanical) platform technology for the generic integration of various packaged MEM devices above standard CMOS. Hermetic packages with sizes up to 1 mm2 and different sealed-in pressures ( ~ 100 kPa and ~ 2 kPa) are demonstrated. The use of a porous cover on top of the release holes avoids deposition inside the cavity during sealing, but leads to a sealed-in pressure of approximately 100 kPa, i.e. atmospheric pressure. Vacuum ( ~ 2 kPa) sealing has been achieved by direct deposition of a sealing material on the SiGe capping layer. Packaged functional accelerometers sealed at around 100 kPa have an equivalent performance in measuring accelerations of about 1 g compared to a piezoelectric commercial reference device. Vacuum-sealed beam resonators survive a 1000 h 85°C/85%RH highly accelerated storage test and 1000 thermal cycles between -40°C and 150°C.

Simultaneous Optimization of the Material Properties, Uniformity and Deposition Rate of Polycrystalline CVD and PECVD Silicon-Germanium Layers for MEMS Applications

The deposition rate is significantly enhanced by utilizing a plasma-enhanced chemical vapor deposition (PECVD) method. This method produces however an amorphous SiGe deposition. To induce crystallization in the bulk PECVD layer it has to be deposited on top of a chemical vapor deposited (CVD) SiGe layer [4] which in itself is deposited on top of a thin PECVD seed layer (see Fig 1). The purpose of the PECVD seed layer is to minimize the incubation time. The CVD and PECVD depositions are performed sequentially in an Applied Materials Centura CxZ chamber.

Improvement of PECVD Silicon–Germanium Crystallization for CMOS Compatible MEMS Applications

This paper investigates the influence of the electrode spacing, chamber pressure, total gas flow, and H 2 dilution on the crystallinity, resistivity, uniformity, and stress of polycrystalline silicon-germanium (poly-SiGe) films grown by plasma-enhanced chemical vapor deposition (PECVD). Boron-doped PECVD SiGe films of 1.6 μm thick are deposited on 400 nm chemical vapor deposition layers from SiH 4 , GeH 4 , and B 2 H 6 precursors. The microstructure is verified by transmission electron microscopy and by X-ray diffraction. It was discovered that for constant temperature and deposition rate, the PECVD SiGe microstructure changes from completely amorphous to polycrystalline by increasing the electrode spacing and pressure due to reduced ion bombardment. A process window of an electrode spacing and pressure for the PECVD poly-SiGe deposition is thus identified based on a sheet resistance mapping method. Increasing the total gas flow dramatically improves the within-wafer crystallinity variation and further reduces the resistivity. Increasing the H 2 flow during PECVD shifts the stress from -51 to 17 MPa and further reduces the crystallinity variation over the wafer. In addition, the effect of changing the SiH 4 to GeH 4 ratio and the in situ boron doping by adding B 2 H 6 is also investigated. The findings in this paper are expected to facilitate the use of poly-SiGe in the above complementary metal oxide semiconductor (CMOS) microelectromechanical system (MEMS) applications.

Improvement of the poly-SiGe electrode contact technology for MEMS

Polycrystalline silicon–germanium (poly-SiGe) has already been shown to be an excellent structural material for microelectromechanical systems. It also enables a monolithic integration with CMOS due to its deposition temperature ≤450 °C. An important factor in the success of this monolithic integration is the electrical resistance between MEMS and CMOS. In this paper the contact resistance between a poly-SiGe MEMS electrode and an Al-top CMOS electrode was investigated using a stacked Greek cross structure. It was significantly reduced by the use of a combined soft sputter etch and a Ti–TiN interlayer. All parameters influencing the contact resistance were identified and taken into account to determine the specific contact resistivity using a simplified model. A very low specific contact resistivity of 3.15 × 10−7 Ω cm2 was achieved on combining an Ar soft sputter etch (20 nm) and a Ti–TiN (5–20 nm) interlayer. The resistivity achieved is better than previously reported values using a complex Ni–silicide process.

Stacked Boron Doped Poly-Crystalline Silicon-Germanium Layers: an Excellent MEMS Structural Material

In this work stacked boron doped poly-crystalline Silicon-Germanium (poly-SiGe) layers, which can be applied as structural MEMS layers, were studied. A standard 1 µm base layer, deposited at 480 oC chuck temperature, is stacked until the required thickness (e.g. 10 x for a 10 µm thick layer). This 1 µm base layer consists of a PECVD seed layer (+/− 75 nm), a CVD crystallization layer (+/− 135 nm) and a PECVD layer to achieve the required thickness with a high growth-rate. The top part of this PECVD layer can optionally be used for optimizing the stress gradient by a stress compensation layer. This approach resulted in 4 µm thick poly-SiGe MEMS structural layers with low tensile stress (50 MPa), low resistivity (2 mΩcm) and a low strain gradient ( −5 /µm).

Influence of the novel anchor design on the shear strength of poly-sige thin film wafer level packages

This paper demonstrates several novel anchor designs for thin film wafer level packaging. Additionally, for the first time, the influence of the anchor design parameters, processing parameters and the choice of the release process on the shear strength of the thin film packages is evaluated. Polycrystalline Silicon-Germanium (poly-SiGe) thin film packages with a sacrificial SiO2 layer are used as test samples. For the majority of the packages the MIL-standard is reached. For the failing packages the cause is identified and understood. Thin film packages with a very small anchor width are strong enough to reach the MIL-standard which leads to smaller packages, less occupied area and thus cost reduction.