Luc Haspeslagh

HIM0S-a high efficiency flash E/sup 2/PROM cell for embedded memory applications

A flash E/sup 2/PROM device which is programmed with a highly efficient hot-electron injection mechanism is described. This high-injection MOS (HIMOS) device combines a very high programming speed at 5-V-only operation with a low development entry cost, which renders it highly attractive for embedded memory applications. The HIMOS concept exhibits complete soft-write immunity and the possibility of overerasure without causing any problem in a memory architecture. It is shown that this device can also operate with a 3.3-V voltage supply, which is of a major importance for the next generation of submicron flash E/sup 2/PROM technologies. >

A new scalable self-aligned dual-bit split-gate charge-trapping memory device

Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating-gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable. Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages.

A highly reliable 3-D integrated SBT ferroelectric capacitor enabling FeRAM scaling

Ferroelectric random access memories (FeRAMs) combine very attractive properties such as low-voltage operation, fast write and nonvolatility. However, unlike Flash memories, FeRAMs are difficult to scale along with the CMOS technology roadmap, mainly because of the decrease of available signal with decreasing cell area. One solution for further scaling is to integrate three-dimensional (3-D) FeCAPs. In this paper, we have integrated a 3-D FeCAP structure in a 0.35-/spl mu/m CMOS technology whereby the effective area of <1 /spl mu/m/sup 2/ single FeCAPs is increased by a factor of almost two. We show that, after optimization of the metal-organic chemical vapor deposition (MOCVD) deposition and post-anneal steps of the Sr/sub 0.8/Bi/sub 2.2/Ta/sub 2/O/sub 9/ (SBT) layer, the sidewall SBT contributes to the polarization Pr, resulting in higher Pr values for 0.81-/spl mu/m/sup 2/ three-dimensional (3-D) capacitors (2Pr/spl ap/15 /spl mu/C/cm/sup 2/) than for 1000 /spl mu/m/sup 2/ 2-D capacitors (2Pr/spl ap/10 /spl mu/C/cm/sup 2/). Moreover, these 3-D capacitors are observed to be fatigue-free and imprint-free up to 10/sup 11/ cycles (5-V square pulses), and extrapolations of retention tests indicate less than 10% Pr loss after ten years at 85/spl deg/C, which shows that sidewall SBT retains the same excellent reliability properties as 2-D capacitors. We demonstrate in this paper that the negative signal-scaling trend can be halted using 3-D FeCAPs. To our knowledge, this paper is the first report on electrical and reliability properties of integrated 3-D FeCAPs, and is a starting point for future development work on densely scaled FeRAMs.

Highly reliable CMOS-integrated 11MPixel SiGe-based micro-mirror arrays for high-end industrial applications

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.

Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention

We describe the low-field leakage through high-k interpoly dielectric stacks in floating gate nonvolatile memories with an inelastic trap-assisted tunneling model, which accounts for arbitrary trap distributions in both energy and space. A systematic investigation of the impact of trap parameters, stack composition, bias and temperature on the leakage is presented, focusing on Al2O3-based stacks. Room- and high-temperature retention data indicate charge loss/gain due to bulk traps in Al2 O3, with an average depth of 2.2 eV and a spread of plusmn0.3 eV. Scalability of Al2O3 IPD stacks below 6.5 nm EOT may be achieved by reducing the trap density by at least 1 order of magnitude

A 5 V-compatible flash EEPROM cell with microsecond programming time for embedded memory applications

This paper presents a split-gate flash EEPROM cell that relies on enhanced hot-electron injection onto the floating gate for fast 5 V-only programming. The device is referred to as the High Injection MOS (or HIMOS) cell and is fabricated in a 0.7-/spl mu/m double polysilicon CMOS technology with minor additions to the standard CMOS process flow. The cell has been optimized for a virtual ground array configuration in order to shrink the area down to the range of 10-20 /spl mu/m/sup 2/ per bit. An extensive study is presented of the influence of applied programming voltages and device geometry on cell performance. It is shown that, for a cell area of 16.5 /spl mu/m/sup 2/, microsecond programming can be achieved with a program-gate voltage of 12 V and 5 V-only operation. Furthermore, during programming the unique features of the HIMOS cell result in very low drain current (approximately 25 /spl mu/A per cell for 5 V-only operation) and a correspondingly low power consumption. It is shown experimentally that the combination of high programming efficiency with low power consumption indicates that 3.3 V-only operation is already viable in 0.7-/spl mu/m technology. In addition, a detailed study of the various possible disturb effects confirms the reliability of the HIMOS technology, and the feasibility of using a virtual ground array for this memory cell. >

Silicon Based System for Single-Nucleotide-Polymorphism Detection: Chip Fabrication and Thermal Characterization of Polymerase Chain Reaction Microchamber

A single nucleotide polymorphism (SNP) is a difference in the DNA sequence of one nucleotide only. We recently proposed a lab-on-a-chip (LoC) system which has the potentiality of fast, sensitive and highly specific SNP detection. Most of the chip components are silicon based and fabricated within a single process. In this paper, the newly developed fabrication method for the silicon chip is presented. The robust and reliable process allows etching structures on the same chip with very different aspect ratios. The characterization of a crucial component to the LoC SNP detector, the microreactor where DNA amplification is performed, is also detailed. Thanks to innovative design and fabrication methodologies, the microreactor has an excellent thermal isolation from the surrounding silicon substrate. This allows for highly localized temperature control. Furthermore, the microreactor is demonstrated to have rapid heating and cooling rates, allowing for rapid amplification of the target DNA fragments. Successful DNA amplification in the microreactor is demonstrated.

Surface-Charge-Collection-Enhanced High-Sensitivity High-Stability Silicon Photodiodes for DUV and VUV Spectral Ranges

The electrical and optical performance of silicon pure-boron (Pure-B) diode is investigated in relationship to the thermal processing used after formation of the PureB chemical-vapor-deposition layer that creates otherwise extremely ultrashallow p+-n junctions. The measured responsivity of PureB diodes is high and stable in the deep ultraviolet (UV) and vacuum UV spectral ranges, covering the spectrum from 220 down to 50 nm. Results are presented, showing that a very high surface charge collection efficiency can be obtained owing to a strong surface electric field resulting from a doping profile that is steep and without roll-off right up to the Si surface.

Al2O3 Based Flash Interpoly Dielectrics: a Comparative Retention Study

In this work the authors present a thorough investigation of charge retention in memory cells with SiO2/Al2O 3 interpoly dielectric (IPD) stacks, using a fully planar stacked gate memory cell with self-aligned floating gate. This structure is interesting for future area scaling and allows high-k materials and metal gates to be easily introduced. It is shown that the retention behaviour is determined by room temperature charge loss and directly correlated to the properties of the IPD layer. From a comparison between different thicknesses, gate materials and post-deposition anneals (PDA) of the Al2O3 layer, it is also found that the bottom oxide thickness is the key parameter for retention, while the use of a poly gate and a low PDA temperature yield further improvement

Simultaneous Optimization of the Material Properties, Uniformity and Deposition Rate of Polycrystalline CVD and PECVD Silicon-Germanium Layers for MEMS Applications

The deposition rate is significantly enhanced by utilizing a plasma-enhanced chemical vapor deposition (PECVD) method. This method produces however an amorphous SiGe deposition. To induce crystallization in the bulk PECVD layer it has to be deposited on top of a chemical vapor deposited (CVD) SiGe layer [4] which in itself is deposited on top of a thin PECVD seed layer (see Fig 1). The purpose of the PECVD seed layer is to minimize the incubation time. The CVD and PECVD depositions are performed sequentially in an Applied Materials Centura CxZ chamber.