Gerald Mittendorfer

Plasma activated wafer bonding : The new low temperature tool for mems fabrication

Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15-30 minutes and up to 2-3 hours. This new technique enables integration of various materials combinations coming from separate production lines.

Metal Thermocompression Wafer Bonding for 3D Integration and MEMS Applications

Due to the diffusion mechanism one of the most important aspects for the bonding process is to control the surface status. Contamination or native oxides may impact consistently on the process result (defect-free, high bond strength and particularly for 3D applications low resistivity). Metal oxides have different behavior and have to be treated accordingly. For example in case of Copper two different approaches are used in order to minimize the oxide-induced issues: metal surface protection with an organic layer (e.g. Benzotriazole) and oxide removal by wet etching or by heated gas treatment (e.g. forming gas). If this method works in case of Copper it doesn’t make it a general rule: in case of Aluminum, the native oxide is chemically very stable and can not be removed as in case of Copper. In such case other methods are employed (e.g. mechanical breakage of oxide).

Reversible wafer bonding for reliable compound semiconductor processing

Reversible wafer bonding is a process enabling reliable compound semiconductor wafer handling for multi-step processes including photolithography, thinning, etching or coating. Two processes using wax and dry film adhesives are presented in this paper.

CMOS wafer bonding for back-side illuminated image sensors fabrication

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing process (adhesive bonding and low temperature plasma activated direct wafer bonding with polymer layers) will be reviewed.

Wafer Bonding for Backside Illuminated CMOS Image Sensors Fabrication

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing process (adhesive bonding and low temperature plasma activated direct wafer bonding with polymer layers) will be reviewed.

Wafer bonding for vacuum encapsulated MEMS

The working principle of various categories of MEMS devices require inside the packages the encapsulation of vacuum ambient which impacts on device performance. The factors impacting on process choice will be reviewed. Main wafer bonding processes used for such applications will be introduced.

Wafer bonding for CMOS integration and packaging

The use of CMOS wafers imposes important limitations for W2W (Wafer-to-Wafer) or C2W (Chip-to-Wafer) bonding: low processing temperature (max. 400°C), no mobile ions and extreme cleanliness. Additional to substrates preparation a special focus is directed on cleaning and maintaining the wafers clean during processing. Special cleaning processes were adopted for CMOS-compatible applications. The main challenges raised by CMOS-compatible wafer bonding in terms of processing and process control were identified and process solutions will be presented illustrated with examples.

Copper-oxide reduction for low-temperature wafer bonding

Silicon wafers with a 500 nm sputtered Cu layer were successfully bonded at low temperatures of 175°C for 30 min in forming gas. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) were used for oxide detection and microstructure imaging.

Wafer bonding for MEMS and CMOS integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.

Spray Coating Technology of Photoresist/Polymer for 3-D Patterning and Interconnect

A relatively little known form of photoresist coating or polymer application for special applications of 3-D structured wafer patterning and interconnection by spray technology has been studied. Specifically, the study was on the OmniSpray coating technology developed by Electronics Vision Group Austria [1,2]. Results of the present investigation confirm the superiority of the technique in comparison with the more conventional spin coating method in term of its ability to cover extreme 3-D structure conformally to enable 3-D patterning, and its significant reduction of expensive high-viscosity photoresist/polymer consumption for 3-D interconnect purposes. Special attention is paid to the improvement of photoresist coverage on the convex corners of the 3-D structure by rounding them off first in a TMAH solution, as well as the uniformity improvements in addition to the lower materials consumption for the application of intermediate layers for wafer interconnect purposes. The integrated method offers an enabling technology for patterning of extensive topography and wafer-level intermediate layer application typically required for a multitude of MEMS structures and designs, novel interconnect structures as well as advanced packaging applications. The method is simple, fast and low-cost in comparison with other photoresist coating techniques available and capable of 3-D structure patterning and interconnect.