Eric Pabo

Wafer bonding with metal layers for MEMS applications

Metal films can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of an eutectic alloy layer or an intermetallic compound. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with special emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.

Wafer Bonding Process Selection

Wafer bonding processes offer valuable solutions not only for MEMS devices but more recently for wafer-level 3D interconnects, advanced packaging and LED applications. The increased complexity of the wafer bonding based applications requires very accurate process design. Unfortunately bonding process selection and design is not always well documented or understood and some important details may not be considered, possibly resulting in major issues during product prototyping or even manufacturing. The main topics to be considered for wafer bonding process selection are summarized and explained.

Cu-Sn transient liquid phase wafer bonding for MEMS applications

The impact of process parameters on final bonding layer quality was investigated for Transient Liquid Phase (TLP) wafer-level bonding based on the Cu-Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal deposition method and the ratio of deposited metal layer thicknesses. Typical failure modes in Inter-Metallic Compound (IMC) growth for the mentioned process and design parameters were identified and subjected to qualitative and quantitative analysis. The possibilities to avoid abovementioned failures are indicated based on experimental results.

Adhesive wafer bonding using photosensitive polymer layers

Adhesive wafer bonding is a technique that uses an intermediate layer for bonding (typically a polymer). The main advantages of using this approach are: low temperature processing (maximum temperatures below 400°C), surface planarization and tolerance to particles (the intermediate layer can incorporate particles with the diameter in the layer thickness range). Evaporated glass, polymers, spin-on glasses, resists and polyimides are some of the materials suitable for use as intermediate layers for bonding. The main properties of the dielectric materials required for a large field of versatile applications/designs can be summarized as: isotropic dielectric constants, good thermal stability, low CTE and Youngs modulus, and a good adhesion to different substrates. This paper reports on wafer-to-wafer adhesive bonding using SINR polymer materials. Substrate coating process as well as wafer bonding process parameters optimization was studied. Wafer bonds exceeding the yield strength of the SINR polymer were accomplished on 150 mm Si wafers. Features of as low as 15 μm were successfully resolved and bonded. A unique megasonic-enhanced development process of the patterned film using low cost solvent was established and proven to exceed standard development method performance. Statistical analysis methods were used to show repeatability and reliability of coating processes.

Wafer bonding for vacuum encapsulated MEMS

The working principle of various categories of MEMS devices require inside the packages the encapsulation of vacuum ambient which impacts on device performance. The factors impacting on process choice will be reviewed. Main wafer bonding processes used for such applications will be introduced.

Processes for the Integration of MEMS and CMOS

Wafer to wafer bonding was an enabling technology for MEMS because it provided the needed protection for the devices by capping them at the wafer level allowing them to survive in the required operating environments such as the automotive environment. The two earliest bonding processes used for this wafer level capping were anodic and glass frit bonding. Due to the constant pressures for cost reduction, size reduction, performance increase, increased integration, and shortened product life cycles the integration of MEMS devices with CMOS based circuitry is increasingly being considered and implemented. Consequentially, bonding, whether wafer to wafer or chip to wafer, has the additional role of being an enabling technology for the integration of CMOS and MEMS device. In this technology, the bond joint typically has multiple roles such as providing mechanical strength, electrical signal conductance, and sealing against various environmental agents or for vacuum encapsulation.

Effect of Process Variables on Glass Frit Wafer Bonding in MEMS Wafer Level Packaging

Among different MEMS wafer level bonding processes glass frit bonding provides reliable vacuum tight seals in volume production. The quality of the seal is a function of both seal glass materials and the processing parameters used in glass frit bonding. Therefore, in this study Taguchi L18 screening Design of Experiment (DOE) was used to study the effect of materials and process variables on the quality of the glass seal in 6” silicon wafers bonded in EVG520IS bonder. Six bonding process variables at three levels and two types of sealing glass pastes were considered. The seals were characterized by Scanning Acoustic Microscopy (SAM), cross sectional Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Analysis (EDAX). The results were quantified into four responses for DOE analysis. Key results are a) peak temperature has the strongest influence on seal properties, b) hot melt paste has significantly lower defects compared to liquid paste, and c) peak firing temperatures can be as low as 400°C under certain conditions.

Wafer bonding process for building MEMS devices

The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

Key enabling processes for more-than-moore technologies

The continuation of Moores law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requiring huge capital investments. 3D-IC with through-silicon via (TSV) interconnects provides another path towards “More Than Moore” with relatively smaller capital investment. Recent announcements from leading image sensor and memory manufacturers show that 3D-ICs are finally moving into high-volume manufacturing (HVM) putting “More Than Moore” in reality. Wafer bonding is the enabling process technology to make this happen. Two of the key wafer bonding techniques - low temperature fusion bonding as well as temporary bonding and de-bonding are the major subject of this contribution, introducing basic process flows and working principles for their CMOS integration.

Advances in spray coating technologies for MEMS, 3DICs and additional applications

Photolithography is a core technology for the manufacturing of complimentary metal oxide semiconductor (CMOS) integrated circuits (IC) and one process step in photolithography is the application of the photoresist. This is normally done using spin coating. Micro electro mechanical system (MEMS) manufacturing leverages the process technologies developed for CMOS manufacturing and therefore spin coating is normally used for the application of photoresist and other materials in the MEMS manufacturing processes. Spin coating is based on depositing the photoresist on the substrate and then rotating or spinning the substrate to leave a thin and uniform layer behind. Spin coating is a very useful and well understood technology but it has fundamental limitations with respect to wafer topography, non-round substrates, fragile substrates, oversized substrates and material consumption.