Thorsten Matthias

Thin wafer processing and chip stacking for 3D integration

The advantages as well as the technical feasibility of through silicon vias (TSV) and 3D integration have been widely acknowledged by the industry. Today the major focus is on the manufacturability and on the integration of all the different building blocks for TSVs and 3D Interconnects. In this paper the advances in the field of thin wafer processing and wafer bonding are presented with emphasis on the integration of all these process steps.

CMOS image sensor wafer-level packaging

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.

Advanced wafer bonding solutions for TSV integration with thin wafers

Due mainly to the thermal budget of CMOS devices, bonding techniques compatible with CMOS processing are limited to direct oxide bonding, metal bonding, adhesive bonding, and various hybrids of those methods. In order to facilitate thin wafer processing with existing fab equipment, we developed total solutions for temporary bonding and debonding of carrier wafers. When it comes to TSV integration, the temporary bonding process based on a spin-on adhesive is becoming the industry standard over that with a lamination tape due to better edge protection, compatibility with topographic surfaces, and better stability at higher process temperatures. The benefits with a newly developed spin-on process include temperature stability over 250°C, compatibility with bumped surfaces, short debonding time, easy thermal release, slide-off debonding, and easy cleanup with polar solvents. It is being proven that our temporary bonding and debonding techniques offer time and cost efficiency for TSV integration processes utilizing existing and established equipment and technologies.

Soft UV-based nanoimprint lithography for large-area imprinting applications

The International Technology Roadmap for Semiconductors (ITRS) lays out a quite challenging path for the further development of the patterning techniques needed to create the ever-smaller feature sizes. In recent years the standard lithography reached its limits due to the diffraction effects encountered and the necessary complexity of compatible masks and projection optics. The restrictions on wavelength, in combination with high process and equipment costs, make low cost, simple imprinting techniques competitive with next generation lithography methods. Nanoimprint Lithography (NIL) is predicted as one candidate for the 32 nm and 22 nm technological nodes according to the ITRS. There are several NIL techniques which can be categorized depending on the process parameters and the imprinting method - either step & repeat or full wafer imprinting. A variety of potential applications has been demonstrated by using Nanoimprint Lithography (e.g. SAW devices, vias and contact layers with dual damascene imprinting process, bragg structures, patterned media) [1,2]. In Soft UV-NIL processes the overlay alignment accuracy was not demonstrated to be prepared for nanoelectronic devices; however other applications are already in high volume manufacturing such as the production of optical components (e.g. micro lenses).

3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding

Many feasibility and design studies during the last years have shown that devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Furthermore, as packaging of the devices is a major cost factor, the possibility to integrate multiple functional entities in one package offers a huge potential for cost reduction. On research level the technical feasibility has been proven for a variety of processes. Todays focus lies on innovative manufacturing technologies and process integration schemes, which meet both, the economic and the technical demands. Stacking of individual chips (both chip-to-wafer and wafer-to-wafer) has the inherent advantage that different functional subsystems like logic and memory can be processed on separate wafers thereby reducing the complexity and the number of process steps greatly. The individual chips can be processed on heterogeneous materials, in different fabs and by different producers. Wafer-level integration has the advantage of higher throughput, enhanced cleanliness and the flexibility that standard fab equipment can be used for further processing. 3D integration applying chip-to-wafer bonding focuses on the yield (“good known die”) and enables to stack dies of different size e.g. several small dies on one big base die. This allows e.g. the integration of a logic device from a 300mm Si wafer with RF devices from a 150mm GaAs wafer. In this paper a higher emphasis lies on the key enabling manufacturing technologies and supported processes.

Room temperature debonding — An enabling technology for TSV and 3D integration

3D stacked ICs (3Ds-IC) have been a hot topic for several years, but recent announcements from leading image sensor and memory manufacturers show that 3Ds-ICs finally move into high volume manufacturing. The main difference between a standard 2D wafer fab and a 3Ds-IC wafer fab is the ability to process both sides of an ultra-thin wafer and to manufacture through silicon vias (TSVs). Wide I/O DRAM is currently targeting 20μm thin wafers. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. However, the cost and cycle time of the main TSV manufacturing process steps etching, barrier/seed layer deposition and plating increases significantly with higher aspect ratio. Thinner wafers enable smaller TSV diameters and lower TSV aspect ratios and thereby enable lower cost for TSV manufacturing [1]. The implementation of thin wafer processing in high volume memory manufacturing has brought a significant change of the requirements. In the past the early adopters of thin wafer processing in the fields of power electronics and compound semiconductors designed the backside process flow around the ability to handle and process a thin wafer. Today stacked memory applications the compatibility with standard processes at highest yield is a must. The thin wafers today usually have microbumps on both sides. To ensure high yield for thermo-compression microbump bonding the thin wafers have to fulfil wafer fab cleanliness requirements after debonding. In a nutshell the industry demands standardized processes for thin wafer handling. The revolutionary ZoneBOND® technology achieves just that — standardized and material independent processes and equipment. Temporary bonding to a rigid support carrier and debonding after backside processing have been used for thin wafer handling/processing for many years. However, so far all the debonding methods imposed severe limitations on the manufacturability. For light induced debonding the carrier had to be transparent and for solvent based debonding the carrier had to be perforated. For thermally induced debonding, “slide-off debonding” the debonding temperature had to be below the reflow temperature of the solder bumps, which limited the maximal process temperature of the adhesive. In the past the debonding method, the adhesive properties and the carrier properties were closely linked to each other. This link between debonding method, adhesive and carrier imposed severe limitations on the manufacturability. With ZoneBOND® technology the debonding process is not at all a function of the adhesive any more — debonding has become a function of the carrier. Figure 1 shows the principle of the ZoneBOND® carrier. The ZoneBOND® carrier has two zones, which differentiate by the degree of adhesion between the adhesive and the carrier. The adhesion in the center zone is reduced, whereas full adhesion is at work in the edge zone. It is important to note that the surface of the device wafer does not have to be treated at all for ZoneBOND®, which makes the technology compatible with any kind of surface passivation. This is especially important with regards to assembly after thin wafer processing. Debonding methods which rely on surface modifications of the device wafer have the inherent risk of causing adhesion problems with the underfill material during die bonding. The debonding method is compatible with bumps or pillars in the bond interface as well as on the backside of the wafer stack. No force is applied on the bumps during debonding which results in very high yields. LowTemp™ ZoneBOND® is a revolutionary breakthrough in thin wafer processing. It enables room temperature debonding, which is independent from the properties of the temporary adhesive. Thereby it enables a standardization of the debonding process and debonding equipment as it is material independent. The ZoneBOND® Open Platform for temporary adhesives enables a versatile supply chain with multiple adhesive suppliers.

Recent advances in submicron alignment 300 mm copper-copper thermocompressive face-to-face wafer-to-wafer bonding and integrated infrared, high-speed FIB metrology

We report on recent experimental studies performed as part of a 3D integrated circuit (3DIC) production-worthy process module roadmap check for 300 mm wafer-to-wafer (WtW) copper-to-copper thermocompression bonding and face-to-face (F2F) aligning. Specifically, we demonstrate submicron alignment capabilities (3sigma alignment variability ∼ 1 µm) post Cu bonding on topography M1V1-to-M2 Cu wafers with no interfacial voids observed and complete Cu interdiffusion, as supported by transmission electron microscopy (TEM) and electron back scatter diffraction (EBSD) data. Also, less than 0.1% clustered voids bonding uniformity were observed on bonded blanket Cu wafers. In addition to bonding quality characterization studies involving scanning acoustic microscopy (SAM) and confocal infra-red (IR) laser scanning microscopy, we report on the development of a prototype integrated IR, highspeed focused-ion-beam (FIB) technique with CAD overlay capabilities that enable the creation of site specific cross-sections and TEM samples to better observe bonding structures of interest.

Thin wafer processing - yield enhancement through integrated metrology

Thin wafer handling and processing is performed by temporary bonding to a rigid carrier wafer. The rigid carrier wafer gives mechanical support during wafer thinning and backside processing. Finally the thin wafer is debonded from the carrier wafer and attached to a dicing tape on film frame. While this technology has been demonstrated for a couple of years now in pilot line and small volume, it is an entirely different story to transfer such a technology to high volume manufacturing (HVM).

Silicon-based wafer-level packaging for cost reduction of high brightness LEDs

High brightness LEDs (HB-LEDs) carry a high prospect for general lighting applications. Competing with the cost/performance ratio of current light sources demands an increase of the overall efficiency as well as the reduction of the device cost. Since packaging accounts for 30%–50% of the cost of HB-LED manufacturing, moving from die-level to wafer-level processes is one likely potential solution for reducing cost per lumen. Silicon-based wafer-level-packaging (WLP), using the established processing technology of the MEMS and IC industry, offers high fabrication reliability, high yield and the direct integration of the driver IC in the package. The already small form factor of WLP can be further reduced using Through-Silicon-Vias (TSV), increasing the maximum amount of chips per wafer. Silicon WLP also offers superior thermal management, with the high thermal conductance of silicon. Redistributing LED dies on silicon wafer submounts, with metal bonding and copper TSVs, further improves the heat conductance away from the active region of the chip, resulting in increased device performance. Wafer-level optics can further improve performance and reduce packaging costs.

Recent progress in thin wafer processing

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D IC. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. While the majority of the device manufacturing steps on the front side of the wafer will be completed with the wafer still at full thickness, it will be temporarily mounted onto a carrier before thinning and processing of the features on its backside. Once the wafer reaches the temporary bonding step, it already represents a significant value, as it has already gone through numerous processing steps. For this reason, inspection of wafers prior to non-reworkable process steps is of great interest. Within the context of Temporary Bonding this consideration calls for inline metrology that allows for detection of excursions of the temporary bonding process in terms of adhesive thickness, thickness uniformity as well as bonding voids prior to thinning of the product wafer. This paper introduces a novel metrology solution capable of detecting all quality relevant parameters of temporarily bonded stacks in a single measurement cycle using an Infrared (IR) based measurement principle. Thanks to the IR based measurement principle, the metrology solution is compatible with both silicon and glass carriers. The system design has been developed with the inline metrology task in mind. This has led to a unique system design concept that enables scanning of wafers at a throughput rate sufficient to enable 100% inspection of all bonded wafers inline in the Temporary Bonding system. Both, current generation temporary bonding system throughputs and future high volume production system throughputs as required by the industry for cost effective manufacturing of 3D stacked devices were taken into account as basic specifications for the newly developed metrology solution. Sophisticated software algorithms allow for making pass/ fail decisions for the bonded stacks and triggering further inspection, processing and / or rework. Actual metrology results achieved with this novel system will be presented and discussed. In terms of adhesive total thickness variation (TTV) of bonded wafers, currently achieved performance values for postbond TTV will be reviewed in light of roadmaps as required by high volume production customers.