Gi-sung Yoon

Lifetime of EUVL masks as a function of degree of carbon contamination and capping materials

Lifetime of EUVL masks which are intentionally contaminated with carbon is investigated by comparing Si and Ru capping layer. Carbon deposition is observed not only on the multilayer, but also on the absorber sidewall of the mask. Deposited carbon on the sidewall during EUV exposure gradually varies mask CD and also induces the changes in the wafer printability and dose in the scanner. In addition, we compare the effects of carbon contamination between Si and Ru capped blank. Ru capped blank shows longer mask mean time between cleaning (MTBC) than Si capped blank by 25% in our experiments.

Improvement in accuracy of defect size measurement by automatic defect classification

The blank mask defect review process involves detailed analysis of defects observed across a substrate’s multiple preparation stages, such as cleaning and resist-coating. The detailed knowledge of these defects plays an important role in the eventual yield obtained by using the blank. Defect knowledge predominantly comprises of details such as the number of defects observed, and their accurate sizes. Mask usability assessment at the start of the preparation process, is crudely based on number of defects. Similarly, defect size gives an idea of eventual wafer defect printability. Furthermore, monitoring defect characteristics, specifically size and shape, aids in obtaining process related information such as cleaning or coating process efficiencies. Blank mask defect review process is largely manual in nature. However, the large number of defects, observed for latest technology nodes with reducing half-pitch sizes; and the associated amount of information, together make the process increasingly inefficient in terms of review time, accuracy and consistency. The usage of additional tools such as CDSEM may be required to further aid the review process resulting in increasing costs. Calibre® MDPAutoClassify™ provides an automated software alternative, in the form of a powerful analysis tool for fast, accurate, consistent and automatic classification of blank defects. Elaborate post-processing algorithms are applied on defect images generated by inspection machines, to extract and report significant defect information such as defect size, affecting defect printability and mask usability. The algorithm’s capabilities are challenged by the variety and complexity of defects encountered, in terms of defect nature, size, shape and composition; and the optical phenomena occurring around the defect [1]. This paper mainly focuses on the results from the evaluation of Calibre® MDPAutoClassify™ product. The main objective of this evaluation is to assess the capability of accurately estimating the size of the defect from the inspection images automatically. The sensitivity to weak defect signals, filtering out noise to identify the defect signals and locating the defect in the images are key success factors. The performance of the tool is assessed on programmable defect masks and production masks from HVM production flow. Implementation of Calibre® MDPAutoClassify™ is projected to improve the accuracy of defect size as compared to what is reported by inspection machine, which is very critical for production, and the classification of defects will aid in arriving at appropriate dispositions like SEM review, repair and scrap.

Extending DUV mask inspection tool for inspecting 2xnm HP and beyond

Advanced 193nm DUV optical inspection tools that can cover 2Xnm HP node become more important and they are being tested to estimate their extendibility. We report DUV based inspection results evaluated and compared to wafer prints, as well as mask CD-SEM images in order to determine the size of printable defects that must be detected in each device node. Applied Materials® advanced Aera™ optical mask inspection tool that adapted a new optical technology enhancement was utilized to evaluate its inspection capability. The illumination conditions and pixel size were optimized to increase inspection sensitivity and reach detection requirements for not only critical defects that print on the wafer but also non-printing defects that indicate to a mask issue. Simulation was used to study suitable optical illumination conditions analyzing results to achieve the best performance for high-end EUV mask inspection toward next generation lithography.

Improving inspectability of sub-2x-nm node masks with complex SRAF

As Moore’s Law continues its relentless march toward ever smaller geometries on wafer, lithographers who had been relying on the implementation of a solution using EUV lithography are faced with increasing challenges to meet requirements for printing sub-2x nm half-pitch (HP). The available choices rely on 193 nm DUV immersion lithography, but with decreasing k1 values and thus shrinking process windows. To overcome these limitations, two techniques such as inverse lithography technology (ILT) and source mask optimization (SMO) were introduced by computational OPC scheme. From a mask inspection viewpoint, the impact of both ILT and SMO is similar – both result in photomasks that have a large quantity of sub-resolution assist features (SRAFs). These SRAFs are challenging for mask-makers to pattern with high fidelity and accuracy across a full-field mask, and thus mask inspection is challenged to maintain a high sensitivity level on primary mask features while not suffering from a high nuisance detection rate on the SRAF features. To solve this particular issue, new inspection approach was developed by using computational image calibration based wafer scanner simulation. This paper will be described the new capabilities, which analyzes the aerial image to differentiate between printing and non-printing features, and applying the appropriate sensitivity threshold. All analysis will be shown comparing results with and without the new capabilities, with an emphasis on inspectability improvements and nuisance defect reduction to improve mask cycle time.

EUV mask inspection study for sub-20nm device

Reflected light inspection has been used to inspect EUVL mask which consists of multi layers and metal absorber. However, sub-wavelength half pitch patterns and reflected inspection make unprecedented phenomenon like tone inversion. These lead EUV inspection more difficult in detectability and inspectability for separating out defects and false. In this study, we report the evaluation result of inspection dependency of illumination conditions like OAI(Off-Axis Illumination), sigma and polarization for sub-20nm EUVL PDM(programmed defect mask). With inspection of sub- 20nm device mask, we finally address the inspection feasibility for sub-20nm device and the future direction of inspection technology.

The application of phase grating to CLM technology for the sub-65nm node optical lithography

As a promising technology for sub-65nm node optical lithography, CLM(Chrome-Less Mask) technology among RETs(Resolution Enhancement Techniques) for low k1 has been researched worldwide in recent years. CLM has several advantages, such as relatively simple manufacturing process and competitive performance compared to phase-edge PSMs. For the low-k1 lithography, we have researched CLM technique as a good solution especially for sub-65nm node. As a step for developing the sub-65nm node optical lithography, we have applied CLM technology in 80nm-node lithography with mesa and trench method. From the analysis of the CLM technology in the 80nm lithography, we found that there is the optimal shutter size for best performance in the technique, the increment of wafer ADI CD varied with patterns pitch, and a limitation in patterning various shapes and size by OPC dead-zone - OPC dead-zone in CLM technique is the specific region of shutter size that dose not make the wafer CD increased more than a specific size. And also small patterns are easily broken, while fabricating the CLM mask in mesa method. Generally, trench method has better optical performance than mesa. These issues have so far restricted the application of CLM technology to a small field. We approached these issues with 3-D topographic simulation tool and found that the issues could be overcome by applying phase grating in trench-type CLM. With the simulation data, we made some test masks which had many kinds of patterns with many different conditions and analyzed their performance through AIMS fab 193 and exposure on wafer. Finally, we have developed the CLM technology which is free of OPC dead-zone and pattern broken in fabrication process. Therefore, we can apply the CLM technique into sub-65nm node optical lithography including logic devices.