Gil Sung Lee

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

In this paper, arch gate silicon–oxide–nitride–oxide–silicon (SONOS) flash memory is studied. The key technology for this device lies in making the device channel on an arch-shaped silicon fin. This feature enhances the electric field across the tunneling oxide by field concentration, and at the same time, reduces the field across the barrier oxide. Thus, when the high gate voltage is applied in the program operation, the tunneling current, and in turn, the program speed is drastically improved. The lowered electric field at the top oxide prohibits the electron back-tunneling from the polycrystalline silicon gate, which enables more reliable and faster erase operation. Full fabrication processes and the measurement results are presented in detail. The process and device simulation results are also given to confirm the critical electrostatic characteristics of the Arch SONOS flash memory device at each step and design the process integration.

A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure

In order to overcome the limitation of a multibit silicon-oxide-nitride-oxide-silicon (SONOS) memory with multistorage nodes, we propose a unique 3-D vertical NOR (U3VNOR) array architecture. The U3VNOR has a vertical channel so that it is possible to have a long enough channel without extra cell area. Therefore, we can avoid the problems such as redistribution of injected charges, second-bit effect, and short-channel effect. Also, it is the most integrated flash architecture having the smallest unit cell size, which is 1 F2/bit. In this paper, we present the fabrication method and the operation voltage scheme of the U3VNOR. In addition, through numerical simulation, we verify its program and erase characteristics. Due to its high density and reliable multibit operation, the U3VNOR is a promising structure for the future high-density NOR flash memory.

Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance

In this letter, a novel SONOS NAND Flash memory array featuring arch-shaped silicon fin and extended word lines (WL) is proposed to improve virtual source/drain (VSD) performance. The arch shape concentrates electric field, resulting in higher electron concentration at the VSD region and higher on -state cell current. In addition, the extended WL process improves the short-channel-effect (SCE) immunity and I-V characteristics. To verify these, an arch VSD NAND array device was fabricated and characterized. The integrated device shows very small SCE while obtaining high on-state cell current. Program and disturbance characteristics of the device are also confirmed.

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon–oxide–nitride–oxide–silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler–Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30×70 nm2 (L×W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7 nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.

Cone-Type SONOS Flash Memory

A novel SONOS Flash memory device, named as a cone-type SONOS memory, is fabricated and analyzed. The main idea of this structure is using a vertical cone-shape silicon channel to improve Flash memory characteristics. By taking advantage of the shape, a great electric-field concentration effect is made. Moreover, the structure has enhanced characteristics of suppressing back-tunneling current. As a result, there are little erase saturation phenomenon and no retention degradation.

Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory

A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F2 size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node

A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.

Locally-separated vertical channel SONOS flash memory (LSVC SONOS) for multi-storage and multi-level operation

A SONOS flash memory having locally-separated vertical channels is investigated. The vertical SONOS flash memory has a scaling issue related with the fin width. As the fin width is shorter, electrical interference between paired cells (PCI) is severer. To overcome PCI, we propose the locally-separated vertical channel SONOS (LSVC SONOS) structure. We demonstrate reliable operation of LSVC SONOS using ATLAS simulation. This device structure is promising for multi-storage and multi-level operation.

Effects of equivalent oxide thickness on bandgap-engineered SONOS flash memory

In order to implement more advanced nonvolatile memory device, many studies have been devoted to improve program/erase speed, endurance, and retention characteristics of nitride-based SONOS flash memory. As the CMOS device size shrinks down, the oxide-nitride-oxide (ONO) multi-layer where charge storage takes place in discrete traps in the silicon nitride layer needs the optimization of thickness and material properties in order for the SONOS flash device to follow the CMOS technology development trend. However, the retention characteristics of SONOS flash memory degrade with the scaling of tunnel oxide, although the program/erase speed is enhanced with the decrease of tunnel oxide thickness. To overcome this problem, we adopted the SONOS structures with bandgap-engineered tunnel oxide layer. The bandgap- engineered SONOS flash memory provides faster erase speed and better retention characteristics than the conventional SONOS flash memory in our previous work. In order to identify the limitation of the equivalent oxide thickness (EOT) of the ultra-thin ONO barrier which replaces the single tunnel oxide layer in the conventional SONOS structures, we have controlled the EOT of the ONO barrier by the standard CMOS process and investigated their effects on the program/erase speed, memory window, and data retention characteristics of the bandgap-engineered SONOS flash memory device. As a result, the experimental data show that the ONO has a degree of freedom in the thickness of each layer but the data retention loss should be still considered. The SONOS flash memory with bandgap engineering by adopting the ONO barrier instead of single tunnel oxide layer should have a lower limit of 3 nm as the EOT for both performance and reliability.

Memory characteristics improvement encouraged by the shape of narrow drain in cone SONOS memory structure

We have proposed cone SONOS memory structure previously. The point of the structure is field concentration effect in two directions. Among the two, concentration of source to drain direction is critical in program operation. Simulation result shows the shape of narrow drain leads to great memory performance. Fabricated structure shows the same results. In this report, simplified program simulation result is presented and great injection characteristics is shown by comparison with cylinder structure.