Maximilien Glorieux

SER/SEL performances of SRAMs in UTBB FDSOI28 and comparisons with PDSOI and BULK counterparts

This work presents alpha and neutron SER characterizations of a 28nm commercial Fully-Depleted SOI technology predisposed to consumer applications. Its intrinsic SER hardness is as well compared to known highly reliable Partially-Depleted SOI technologies.

New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level

A new latch architecture based on a switchable hysteresis mechanism to improve the SEU hardness in hold mode and limit the delay penalty during write operation is proposed. This latch relies on the Schmitt trigger inverter schematic and has been named the Robust Schmitt Trigger (RST) latch. RST latch has been implemented in a 65 nm radiation test vehicle and upset rates have been measured during proton irradiations. Our design solution enhanced the SEU cross-section and divides by 2 the system level power consumption penalty compared to a DICE based design. The RST latch is an alternative between the DICE latch and the reference latch for soft radiative environments.

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

This paper shows alpha and neutron experimental Soft Error Rate characterization of a SRAM test vehicle processed with different process corners in order to emulate the variability encountered in volume production. It allows assessing large variability effects with few samples that are compatible with accelerated SER testing. This allows investigating the effect of variability in mass-production on soft error rate of deca-nanometric technologies.

Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor

In this paper, we present the heavy-ion radiation test results for a 7-stage SPARC micro-processor. Special software handlers enabled fine grained classification of the types of crashes. The measured crash cross sections are compared with those predicted by fault injection simulation.

Experimental Soft Error Rate of Several Flip-Flop Designs Representative of Production Chip in 32 nm CMOS Technology

This paper shows alpha experimental Soft Error Rate characterization of several standard and hardened Flip-Flop architectures processed in a 32 nm technology. It showsthe effecton the alpha Soft Error Rateof experimental parameters such as algorithm (static vs.kdynamic), data filling the register, etc. 12 data patterns onmore than 5Flip-Floptypes(including DICE-like design)are reported in this articlein order to help the radiation engineer to choose the best algorithm/pattern for its SER characterizations.

Space radiation and reliability qualifications on 65nm CMOS 600MHz microprocessors

Recent space programs have reached the limits of the current space digital ASIC offers, mainly relying on CMOS 180nm. The new ST CMOS 65nm space program described in this paper shows how those limits are overcome. Small modifications to the commercial bulk process, paired with cost effective design reinforcements allow higher density and better energy efficiency while ensuring a strong space-grade resilience. The implementation of a 32-bit SPARC LEON3 microprocessor demonstrates the capabilities of this new technology.

Process Variability Effect on Soft Error Rate by Characterization of Large Number of Samples

For the first time die-to-die soft error rate (SER) variability from process manufacturing is experimentally characterized by irradiating a very large number of samples from a single wafer. Alpha and neutron SER is measured and reported as a function of original location on wafer, test dates and samples capacity. CAD tools are then used to evaluate their capacity to assess die-to-die alpha and neutron SER variability.

Detailed SET Measurement and Characterization of a 65 nm Bulk Technology

Single Event Transients (SETs) are a major concern for space applications, particularly when hardened flip flops are used to reduce the sensitivity of sequential logic. Characterizing SETs is complex as both the cross section and the pulse width must be measured. In the 65 nm test chip presented in this paper, three different SET measurement circuits, implemented on the same die, are characterized and compared. Using these SET detectors, heavy-ion test results are presented. The detectors are compared and a detailed study of the SET sensitivity of multiple gates operating at different logical, load and voltage conditions is presented.

Random-Walk Drift-Diffusion Charge-Collection Model For Reverse-Biased Junctions Embedded in Circuits

A new computational model for charge transport based on parallelized random-walk drift-diffusion is proposed. This approach models the radiation-induced charge carriers as charge packets in a 3-D structure and the transport modeling are based on simple physical equations without any fitting parameter. This model has been dynamically coupled with a SPICE circuit simulator to take into account temporal variations of the electric fields in the charge collection process. Thus, the circuit electrical response modulates the charge collection efficiency. Three simulation cases have been explored and compared with TCAD simulations or radiation experiments in 65 nm technology to validate the accuracy of the proposed approach. These simulations demonstrate the capability of the proposed model to accurately estimate the soft error rate of complex structures, such as flip-flops over a large range of ionizing particle linear energy transfer. The proposed simulation methodology is also able to take into account charge-sharing phenomenon, and this point is highlighted by a specific investigation on the considered flip-flop.

Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits

Abstract This work describes a new computational approach for modeling the radiation-induced transient current and charge collection at circuit-level. Our methodology is based on a random-walk process that takes into account both diffusion and drift of radiation-induced minority carriers in a non-constant electric field both in space and time. The model has been successfully coupled either with an internal routine or with SPICE for circuit solving and feedback on the charge-collection process. It is illustrated here for a junction impacted by an ionizing particle and embedded in a CMOS inverter.