Tae-Seong Jang

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3.2Gb/s/pin. Our LPDDR4 DRAM offers 2× bandwidth with improved power efficiency over LPDDR3 SDRAMs, due to the 2-channel architecture and low-voltage-swing terminated logic (LVSTL) [1]. Moreover, the supply voltage is further reduced to 1.0V in this work, 0.1V lower than the LPDDR4 standard, for extra power saving.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for DQS tree delay tracking. This chip is fabricated in 25 nm DRAM process on 88.1 mm 2 die area.