Youn Sung Choi

Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

The impact of isolated and arrayed 10×60μm via-middle Cu TSVs on 8LM 28nm node CMOS poly-SiON P/NFETs was electrically measured for proximities >;4 μm at 27C and 105C. The largest observed shift in Ion (<;2.3%) is significantly less than that from other context-dependent sources such as dual stress liner boundaries (~10%). NanoBeam Diffraction measurements of Si strain within 5μm of TSVs were acquired for samples prepared from fully processed wafers, showing that for proximity >;1.5μm the impact of TSVs is negligible. Interaction with overlying interconnect is mitigated through optimization of post-TSV plating anneal to achieve <; 200 ÅCu pumping and by introducing a TSV unit cell designed to minimize the impact on local environment.

Layout Variation Effects in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect

This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction.

Pocket Implant-Dependent Channel Mobility in Advanced p-MOSFETs With Strain Engineering

A new approach to channel mobility engineering using strained-Si technology is described with a complete data analysis. It is discussed that [110]/(100) Si channel mobility in p-MOSFET with embedded SiGe source/drain and compressive stress liner can be strongly dependent on pocket implant dose, resulting from a change in piezoresistance coefficient as a function of p-type carrier dopant concentration in the vicinity of the channel, whereas channel mobility of n-MOSFETs shows weaker dependence on pocket implant dose due to: 1) smaller piezoresistance coefficient of n-channel and 2) less channel strain relative to p-MOSFETs.

Strain Profiles in Si Channel of PMOS Devices Affected by Shallow-Trench Isolation Strain Relaxation In Embedded SiGe

Shallow-trench isolation (STI) induced strain in the moat of Si has been studied extensively by using transmission electron microscopy (TEM) based techniques, such as Convergent Beam Electron Diffraction [1] and dark-field electron holography [2]. However the STI proximity effect on the strain in strained Si devices with embedded SiGe (eSiGe) Source/Drain (S/D) has not yet been analyzed. Also the shape of eSiGe S/D is critical to channel strain for advanced technology. In this report, we used NanoBeam Diffraction (NBD) and Geometric Phase Analysis (GPA) to study the channel strain distribution effect by STI proximity, and the shape of eSiGe S/D.