Michael J. Degerstrom

Accurate resistance, inductance, capacitance, and conductance (RLCG) from uniform transmission line measurements

Existing time-based and frequency-based RLCG extraction methods from measurements on uniform transmission lines are discussed. Using a THRU bisect de-embedding technique proved useful in removing resonances, particularly with the distributed resistance.

Emerging multigigahertz digital and mixed-signal integrated circuits targeted for military applications: dependence on advanced electronic packaging to achieve full performance

A revolution is occurring in several device and integrated circuit technologies (silicon CMOS and its extensions such as silicon germanium and silicon on insulator [SOI] and the so-called III-V compound semiconductors including indium phosphide and gallium arsenide), as well as in solid-state sensors such as infrared detectors enabled by the new materials and devices. These new components are being used to enhance the performance of many systems, and even to create systems never before available, of present interest to the U.S. Department of Defense and of likely near-term interest to parts of the commercial electronics industry such as the landline, wireless, and satellite telecommunications industry. These new components require advanced electronic packaging that does not restrict or degrade their performance. Unfortunately largely due to commercial cost pressures, research in and small-lot manufacture of high-performance packaging though still feasible and not lacking for good ideas for possible enhancement, are no longer being actively pursued either by the principal U.S. government agencies (e.g., DARPA, Air Force), by the commercial electronic packaging industry, or by commercial consortia such as the Microelectronics and Computer Technology Corporation (defunct as of June 2000), Semiconductor Research Corporation (SRC), or Sematech Inc. This paper discusses recent examples of high-performance components and integrated circuit technologies and describes how they are being exploited in new or upgraded systems. Advances in packaging technology that will be required to support the new integrated circuits are also described. In conclusion, several possible approaches are reviewed by which the United States can regain momentum in the development of performance-driven packaging technologies.

An 8-bit 2.5 gigasample A/D converter multichip module for all-digital radar receiver for AN/APS 145 radar on Navy E2-C Airborne Early Warning Aircraft

This paper will discuss multichip module (MCM) technology as it is applied to a prototype high performance direct digitizing channelized radar receiver system under development for the Navys E2-C Airborne Early Warning Aircraft, which encompasses both analog signals at UHF frequencies and multi-gigahertz digital signals. Critical issues which arise in the design of such a system will be discussed, including thermal management, transmission line, voltage standing wave ratio, and simultaneous switching noise analyses. This paper will also describe the various simulation and analysis software tools employed in the development of the MCM containing the analog-to-digital converter (A/D converter) and demultiplexer for this system, and the roles of these tools in providing insight into the design of the MCM.

System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications

Weave-induced skew on printed wiring boards (PWB) for 10+ Gbps SerDes data rates can be very significant. In this paper, we not only investigate weave-induced skew but also look at other sources of skew. We show the weave skew results taken from measurements of three different test boards. Results from a fourth board are presented to examine PWB differential via skew. Measurements from a fifth board are analyzed to determine total channel skew. We propose a budget such that a certain amount of skew can be tolerated with a small increase in channel insertion loss. We then present a case study to project overall performance on PWB yield. We observe a number of anomalies with our test results and suggest additional studies to guard against unpredicted high skew.

PCB pin-field considerations for 40 Gb/s SerDes channels

Designing pin-fields and related structures will be challenging for emerging 40 Gb/s electrically-based SerDes links. It is not known whether pin-fields implemented in conventional printed circuit board (PCB) technology will be capable of supporting these high data rates. We demonstrate through modeling and measurements that PCB pin-fields appear viable for data rates up to 40 Gb/s, provided that care is taken in the design.

Automating pin field modeling for serdes channel simulations

The demands for higher serializer-deserializer (SerDes) data rates dictate the need for more accurate channel models. Assuming that component models are supplied by the vendor, then the printed wiring board (PWB) pin fields are frequently by far the most challenging models for a designer to generate. To greatly reduce the effort required for pin field modeling, automation of the model build process was undertaken. A useful automation script was realized by following a comprehensive set of requirements. Several examples illustrate the utility of this pin field modeling script.

HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY

Under the auspices of Defense Advanced Research Project Agencys Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

System-level exhaustive link simulation needed for PCB Co-design

Traditionally, the large number of high-speed serial links in large, massively-parallel, highly-interconnected computer systems have been analyzed in terms of signal integrity by selecting a small subset of representative links. Co-design decisions on PCB geometries and connectors are often made from this subset of the links. Is that approach adequate? We show the benefit of simulation of all the links in a system. In addition, we demonstrate how exhaustive simulations are possible through a process of automation.

Electronic packaging for 10-100 Gb/s OE systems

The minimization of discontinuities in controlled-impedance signal interconnect will be discussed, including novel ideas for extending present packaging fabrication and assembly technology to higher frequency operation.