Tony Quach

Wet Chemical Digital Etching of GaAs at Room Temperature

A new room temperature wet chemical digital etching technique for GaAs is presented which uses hydrogen peroxide and an acid in a two‐step etching process to remove GaAs in approximately 15 A increments. In the first step, GaAs is oxidized by 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of 14 to 17 A for time periods from 15 to 120 s. The second step removes this oxide layer with an acid that does not attack unoxidized GaAs. These steps are repeated in succession until the desired etch depth is obtained. Experimental results are presented for this digital etching technique demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Ultrahigh-efficiency power amplifier for space radar applications

This paper describes a broad-band switch mode power amplifier based on the indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. The amplifier combines the alternative Class-E mode of operation with a harmonic termination technique that minimizes the insertion loss of matching circuitry to obtain ultrahigh-efficiency operation at X-band. For broad-band Class-E performance, the amplifiers output network employs a transmission line topology to achieve broad-band harmonic terminations while providing the optimal fundamental impedance to shape the output current and voltage waveforms of the device for maximum efficiency performance. As a result, 65% power-added efficiency (PAE) was achieved at 10 GHz. Over the frequency band of 9-11 GHz, the power amplifier achieved 49%-65% PAE, 18-22 dBm of output power, and 8-11 dB gain at 4 V supply. The reported power amplifier achieved what is believed to be the best PAE performance at 10 GHz and the widest bandwidth for a switch-mode design at X-band.

X-band two-stage high-efficiency switched-mode power amplifiers

This paper presents efficiency optimization of X-band two-stage microwave power amplifiers (PAs) in which the output stage is designed to operate in class-E mode. A hybrid PA which uses the same MESFET devices in both stages achieves 16 dB of saturated gain with an output power of 20 dBm and total power added efficiency (PAE) of 52% at 10 GHz. A broadband monolithic two-stage double heterojunction bipolar transistor PA, fabricated by Northrop Grumman Space Technology, with a class-AB first stage and class-E second stage achieves 24.6 dBm of output power with 24.6-dB gain and total PAE of 52% at 8 GHz. The design is performed starting from class-E theory and using load-pull measurements and/or nonlinear simulations.

Mixed-Signal SoCs With In Situ Self-Healing Circuitry

This article discusses the goals and recent achievements of the HEALICs program. The programs aim is to enhance wireless systems with sensors, actuators, and mixed-signal control loops in order to improve their performance yield.

A −189 dBc/Hz FOM T wide tuning range Ka-band VCO using tunable negative capacitance and inductance redistribution

An ultra wideband LC voltage-controlled oscillator (LC-VCO) operating in the Ka-band with equally spaced sub-band coarse tuning characteristics is proposed and characterized. A tunable negative capacitance (TNC) circuit technique is used to cancel the fixed capacitance in the LC-tank to extend the tuning range (TR). A digitally-switched varactor coarse tuning structure with an inductance redistribution technique is utilized to reduce VCO gain (KV) and retain uniform spacing between tuning curves. The proposed VCO structure and a baseline VCO are fabricated in a 130 nm CMOS process. Compared to the reference VCO, the proposed VCO achieves a 34% increase in TR with maximum KV of 450 MHz/V. The measured worst-case phase noise is -100.1 dBc/Hz at 1 MHz offset across the TR from 30.5 GHz to 39.6 GHz. The power dissipation of the VCO core is 11 mW from a 1.2 V supply. The TNC-based VCO achieves a FOMT of -189 dBc/Hz, which is the highest reported at the Ka-band.

Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits

We present an experimentally validated capacitance cancellation structure to increase the tuning range (TR) of LC voltage-controlled oscillators (VCOs) with minimal phase noise or power impact. The cancellation is based on an ultrawideband differential active negative-capacitance (NC) circuit. An NC scheme suitable for bottom-biased VCOs is analyzed and combined with a CMOS VCO to cancel the fixed capacitance in the LC tank. The NC structure is further modified to be tunable, enabling additional expansion of the VCO TR. By manipulating the quality factor (Q) of the NC tuning varactor pair, a prototype VCO achieves a maximum TR of 27% in a 130-nm technology, while dissipating 13 mA from a 0.9-V supply. The TR is the highest reported at Q-band, covering from 34.5 GHz to 45.4 GHz. Compared to the reference VCO without an NC circuit, the TR is increased by 38%. The measured worst case phase noise is -95 dBc/Hz at 1-MHz offset, and the FOMT is -184.9 dBc/Hz.

Design of Wide Tuning-Range mm-Wave VCOs Using Negative Capacitance

Negative capacitance (NC) circuits of single-ended and differential topologies are presented, analyzed and characterized. The novel NC designs extend the bandwidth of conventional NC circuits while maintaining low power consumption. To compare the performance of the designs, a figure of merit (FOM) is proposed. A power and area efficient NC scheme employing a 130 nm CMOS technology is applied to a mm-wave LC Voltage Controlled Oscillator (LC-VCO) for demonstration. The VCO tuning range is extended by employing the NC circuit to cancel the parasitic capacitance of the LC-tank; resulting in a 35% tuning range increase as compared to the reference LC-VCO circuit. The NC-based LC-VCO achieved a 27% tuning range in the Q-Band, which is the highest reported. Measured results compare closely to the theoretical analysis of the LC-VCO operating from 34.5-45.4 GHz.

An indium phosphide X-band class-E power MMIC with 40% bandwidth

A broadband, high efficiency, X-band power amplifier is presented in this paper. The single-stage amplifier is based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. In order to obtain high efficiency operation, a switch mode, class-E amplifier topology was selected. Special attention has been paid to providing the required fundamental matching conditions, as well as appropriate harmonic terminations, over the frequency band of interest. As a result, the amplifier obtained a bandwidth of 40%, with 45-60% PAE, 19-21.5dBm Pout, and 9-11.5dB large-signal gain at X-band. To the best of our knowledge, this circuit demonstrates the widest bandwidth for a class-E amplifier at X-band.

A Time-Interleaved Multimode

A multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. Unlike embedded-mixer ΔΣ RF-DACs which require analog I/Q combining and precise alignment of the local oscillator (LO) and data clock, the proposed circuit is fully digital with only one clock frequency (fS). This architecture eliminates the need for a widely-tuned LO by reconfiguring the ΔΣ modulator (DSM) for a variety of output frequencies, thus making it suitable for software-defined radio. Both a band-pass (BP) and high-pass (HP) DSM are used to synthesize signals at fS/4, fS/2, or 3fS/4. Interleaving is used to reject the first DAC image, doubling the usable bandwidth of the HP DSM while reducing reconstruction filter requirements. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS. With an fS of 2 GHz, the 0.18 mm2 RF-DAC core consumes 55 mW with output powers of -4.5 dBm, -7.5 dBm, and -13.8 dBm at 0.5 GHz, 1 GHz, and 1.5 GHz, respectively. For the HP DSM, a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50 MHz bandwidth, and an in-band SFDR of 58.5 dB are demonstrated.A multimode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (f8) and provides a ΔΣ modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around f8/4, f8/2, or 3f8/4. The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit f8 rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of 0.563 mm2. Measurements at f8 = 2 GHz yield an output power of -0.6 dBm with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR, and -66.4 dBc LTE ACLR. Changing f8 to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of -16.6 dBm, 65.2 dB SFDR, -62 dBc IM3, -59.3 dB WCDMA ACLR, and -59.2 dBc LTE ACLR.

\Delta\Sigma

Current advancements in military and wireless applications create the need for increased functionality with reduced cost and size. In this paper a highly integrated tunable electronics are necessary to meet these new requirements. Barium strontium titanium oxide (BST) is a viable technology for these applications. BST technology offers significant benefits with its high tuning range, high power capabilities and low control voltages. While there is great interest in the development of BST technology, little research has been published regarding integrated matching networks using BST thin film parallel plate capacitors for an X-band low noise amplifier (LNA).