Jamin J. McCue

Systematic Analysis of Interleaved Digital-to-Analog Converters

A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.

A −189 dBc/Hz FOM T wide tuning range Ka-band VCO using tunable negative capacitance and inductance redistribution

An ultra wideband LC voltage-controlled oscillator (LC-VCO) operating in the Ka-band with equally spaced sub-band coarse tuning characteristics is proposed and characterized. A tunable negative capacitance (TNC) circuit technique is used to cancel the fixed capacitance in the LC-tank to extend the tuning range (TR). A digitally-switched varactor coarse tuning structure with an inductance redistribution technique is utilized to reduce VCO gain (KV) and retain uniform spacing between tuning curves. The proposed VCO structure and a baseline VCO are fabricated in a 130 nm CMOS process. Compared to the reference VCO, the proposed VCO achieves a 34% increase in TR with maximum KV of 450 MHz/V. The measured worst-case phase noise is -100.1 dBc/Hz at 1 MHz offset across the TR from 30.5 GHz to 39.6 GHz. The power dissipation of the VCO core is 11 mW from a 1.2 V supply. The TNC-based VCO achieves a FOMT of -189 dBc/Hz, which is the highest reported at the Ka-band.

Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits

We present an experimentally validated capacitance cancellation structure to increase the tuning range (TR) of LC voltage-controlled oscillators (VCOs) with minimal phase noise or power impact. The cancellation is based on an ultrawideband differential active negative-capacitance (NC) circuit. An NC scheme suitable for bottom-biased VCOs is analyzed and combined with a CMOS VCO to cancel the fixed capacitance in the LC tank. The NC structure is further modified to be tunable, enabling additional expansion of the VCO TR. By manipulating the quality factor (Q) of the NC tuning varactor pair, a prototype VCO achieves a maximum TR of 27% in a 130-nm technology, while dissipating 13 mA from a 0.9-V supply. The TR is the highest reported at Q-band, covering from 34.5 GHz to 45.4 GHz. Compared to the reference VCO without an NC circuit, the TR is increased by 38%. The measured worst case phase noise is -95 dBc/Hz at 1-MHz offset, and the FOMT is -184.9 dBc/Hz.

Design of Wide Tuning-Range mm-Wave VCOs Using Negative Capacitance

Negative capacitance (NC) circuits of single-ended and differential topologies are presented, analyzed and characterized. The novel NC designs extend the bandwidth of conventional NC circuits while maintaining low power consumption. To compare the performance of the designs, a figure of merit (FOM) is proposed. A power and area efficient NC scheme employing a 130 nm CMOS technology is applied to a mm-wave LC Voltage Controlled Oscillator (LC-VCO) for demonstration. The VCO tuning range is extended by employing the NC circuit to cancel the parasitic capacitance of the LC-tank; resulting in a 35% tuning range increase as compared to the reference LC-VCO circuit. The NC-based LC-VCO achieved a 27% tuning range in the Q-Band, which is the highest reported. Measured results compare closely to the theoretical analysis of the LC-VCO operating from 34.5-45.4 GHz.

A Time-Interleaved Multimode

A multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. Unlike embedded-mixer ΔΣ RF-DACs which require analog I/Q combining and precise alignment of the local oscillator (LO) and data clock, the proposed circuit is fully digital with only one clock frequency (fS). This architecture eliminates the need for a widely-tuned LO by reconfiguring the ΔΣ modulator (DSM) for a variety of output frequencies, thus making it suitable for software-defined radio. Both a band-pass (BP) and high-pass (HP) DSM are used to synthesize signals at fS/4, fS/2, or 3fS/4. Interleaving is used to reject the first DAC image, doubling the usable bandwidth of the HP DSM while reducing reconstruction filter requirements. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS. With an fS of 2 GHz, the 0.18 mm2 RF-DAC core consumes 55 mW with output powers of -4.5 dBm, -7.5 dBm, and -13.8 dBm at 0.5 GHz, 1 GHz, and 1.5 GHz, respectively. For the HP DSM, a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50 MHz bandwidth, and an in-band SFDR of 58.5 dB are demonstrated.A multimode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (f8) and provides a ΔΣ modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around f8/4, f8/2, or 3f8/4. The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit f8 rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of 0.563 mm2. Measurements at f8 = 2 GHz yield an output power of -0.6 dBm with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR, and -66.4 dBc LTE ACLR. Changing f8 to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of -16.6 dBm, 65.2 dB SFDR, -62 dBc IM3, -59.3 dB WCDMA ACLR, and -59.2 dBc LTE ACLR.

\Delta\Sigma

In this paper, we present an analytical model for predicting the tuning range of CMOS mm-wave LC voltage-controlled oscillators (LC-VCOs). A detailed analysis of the frequency dependent quality factor (Q) of the LC-tank is performed to characterize the tank loss. The frequency dependent Q is used to size the transconductance (gm) of the cross-coupled pair to satisfy the VCO startup condition. The relationship between the cross-coupled pair gm and the operating frequency is also derived. With the above relationships, the frequency dependent tuning range is further calculated and compared with simulation results. To verify the analysis, three CMOS mm-wave VCOs are fabricated in a 130 nm CMOS process. The measured tuning range of the 26 GHz, 34 GHz and 40 GHz VCO is 25%, 21% and 18%, respectively, which is consistent with the presented tuning range model.

RF-DAC for Direct Digital-to-RF Synthesis

In this paper, a double-balanced Gilbert cell down-conversion mixer is demonstrated from 70-110 GHz. The wide bandwidth and high frequency are enabled by the HRL InP/Si BiCMOS process. With an fT of 300 GHz, the available 0.25 μm InP HBTs are used in the signal path while the 90 nm CMOS devices are used for biasing and gain adjustment. The fully differential circuit is implemented using two on-chip Marchand baluns feeding both the LO and RF ports. An IF buffer follows the mixer to improve matching and signal quality for testing. After de-embedding the balun and IF buffer, the mixer core achieves a peak conversion gain of 13 dB, a minimum DSB NF of 10 dB, and an OP1dB of -2 dBm while consuming 5 mA from a 3.3 V supply.

Analytical and experimental study of tuning range limitation in mm-wave CMOS LC-VCOs

The push towards mm-wave frequencies has increased the demand for UWB DACs with minimal spurious emissions. At mm-wave, intra-DAC dynamic timing and data errors consume a significant portion of the clock period, degrading SFDR. Previously, NRZ and RZ DACs have been reported with output frequencies up to 27GHz [1–4]. However, their outputs are limited to the first two Nyquist zones, requiring high sample rates which exacerbate dynamic errors. Interleaved DACs allow for synthesis above the first Nyquist zone without increasing the sample rate, although inter-DAC amplitude and timing errors introduce additional spurs at the output that can limit SFDR [5,6]. Alternatively, mixing DACs decouple the sample rate and output frequency, however, they do not deglitch the output, limiting SFDR at high frequency [7]. The multiple return-to-zero (MRZ) architecture mitigates the effects of dynamic errors in the data path, allowing for synthesis up to 9.45GHz with 42dB SFDR [8]. Moreover, the use of R-2R networks achieves binary scaling with the same unit cell current, alleviating switch timing mismatches. Although these techniques improve the intrinsic SFDR of the DAC cells, mismatches in the frequency response of routing interconnects dominate the performance at mm-wave. This is especially critical for the output summing node, which requires an identical amplitude and phase response from each cell to the output. Previously reported DACs used simple structures to combine currents at the output, resulting in large phase and amplitude mismatches. Furthermore, the mm-wave operation of the RZ clock exacerbates the effect of timing errors due to both interconnect and transistor mismatches in the RZ path.

An Active Double-Balanced Down-Conversion Mixer in InP/Si BICMOS Operating from 70-110 GHz

A multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. Unlike embedded-mixer ΔΣ RF-DACs which require analog I/Q combining and precise alignment of the local oscillator (LO) and data clock, the proposed circuit is fully digital with only one clock frequency (f S ). This architecture eliminates the need for a widely-tuned LO by reconfiguring the ΔΣ modulator (DSM) for a variety of output frequencies, thus making it suitable for software-defined radio. Both a band-pass (BP) and high-pass (HP) DSM are used to synthesize signals at f S /4, f S /2, or 3f S /4. Interleaving is used to reject the first DAC image, doubling the usable bandwidth of the HP DSM while reducing reconstruction filter requirements. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS. With an f S of 2 GHz, the 0.18 mm2 RF-DAC core consumes 55 mW with output powers of −4.5 dBm, −7.5 dBm, and −13.8 dBm at 0.5 GHz, 1 GHz, and 1.5 GHz, respectively. For the HP DSM, a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50 MHz bandwidth, and an in-band SFDR of 58.5 dB are demonstrated.

16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR

Meeting the pressing power and bandwidth requirements of modern communication systems requires the development of highly efficient reconfigurable transceivers. On the receiver side, we present a new class of reconfigurable receiver that utilizes random projections to balance the power-bandwidth tradeoff. Such random projection front-ends are ubiquitous and allow the use of sub-Nyquist ADCs. These systems utilize high speed DACs, typically found in transmitters, to generate high fidelity random signals. The emergence of RF-DACs, used for direct digital-to-RF synthesis, can be leveraged for random projection reconfigurable receivers. However, the need for high output power and linearity in both the transmitter and receiver DACs forces an evaluation of RF-DAC topologies with respect to drain efficiency. In this paper, the power efficiencies of several RF-DAC topologies are compared.