Cheng-Ting Chung

First experimental Ge CMOS FinFETs directly on SOI substrate

High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L_channel =120nm and Fin width=40nm with high I_on/I_off ratio (>10⁵), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S.S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L_channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.

Germanium N and P Multifin Field-Effect Transistors With High-Performance Germanium (Ge)

We demonstrate the characteristics of p⁺-Ge/n-Si and n⁺-Ge/p-Si heterojunction diodes formed by heteroepitaxial Ge grown on Si leading to high performance and very low leakage current. The ON/OFF current ratio of the p⁺-Ge/n-Si and n⁺-Ge/p-Si heterojunction was > 10⁷ and > 10⁶, respectively. The OFF current density was extremely low at <; 10 μA/cm² for the p⁺-Ge/n-Si formed with different implantation energies of 10-40 KeV and ~ 20 μA/cm² for the n⁺-Ge/p-Si with different implantation energies of 20-50 KeV at a reverse bias of |<i>V</i>_R| = ±1 V, respectively. Both p and n-Ge channel multifin field-effect transistors (FinFETs) were formed by a mesa structure using these p⁺-Ge/n-Si and n⁺-Ge/p-Si heterojunctions. A high-κ/metal gate stack was employed. The body-tied Ge multifin FinFET with a fin width (<i>W</i>_Fin) of ~ 40 nm, and the channel length (L_Channel) was 150 nm for p-FinFET and of 110 nm for n-FinFET, exhibiting a driving current of 174 μA/μm at <i>V</i>_G=-2 V and 102 μA/μm at <i>V</i>_G=2 V , respectively. This is the first experimental demonstration of a body-tied high mobility Ge channel multifin FinFET using a top-down approach.

{\rm p}^{+}/{\rm n}

In this letter, we present a high performance Ge n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiGe Schottky junction source/drain fabricated using phosphorus dopant segregation. Phosphorus atoms were implanted into NiGe and then driven toward the NiGe/p-Ge interface to depin the Fermi level and form a Schottky junction. A high effective barrier height (Φ_Bp) of 0.57 eV, resulting in a high junction current ratio of at the applied voltage |V_a| = ±1 V. The nMOSFET exhibited a high I_ON/I_OFF ratio of ~ 8×10³ (I_D), ~ 10⁵ (I_S), and a subthreshold swing of 138 mV/decade. The nMOSFET developed in this letter exhibited greater transconductance and a drain leakage current that is more than two orders of magnitude lower compared with nMOSFETs with the conventional n⁺/p junction.

and

Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high <i>I</i>_ON/<i>I</i>_OFF ratio (~5×10⁵, at <i>VD</i>=0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (<i>V</i>_TH) shift can be maintained at the level of ~110 mV/V and ~ 0.1 V, respectively, for Ge n-channel FinFET with <i>L</i>_channel=120 nm and <i>W</i>_Fin=40 nm. Multifin Ge FinFET with <i>L</i>_channel=170 nm and <i>W</i>_Fin=50 nm is also illustrated. Both <i>N</i>- and <i>P</i>-FinFETs possess high <i>I</i>_ON/<i>I</i>_OFF ratio over 10⁴. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.

{\rm n}^{+}/{\rm p}

We fabricated body-tied Ge p-channel fin field-effect transistors (p-FinFETs) directly on a Si substrate with a high-κ/metal gate stack. This scheme is fully compatible with Si standard processing. The FinFET structure has excellent control on the channel potential and thus can improve the short-channel effect. The diode with p⁺-Ge/n-Si heterojunctions illustrates a remarkably high I_ON/I_OFF >; 10⁶ despite the presence of misfit dislocations at the interface. The high-hole-mobility body-tied Ge p-FinFETs with a fin width <i>W</i>_Fin of ~ 40 nm and a mask channel length <i>L</i>_Mask of 120 nm depict a driving current of 22 μA/μm at <i>VG</i> = -2V and a low off-current of 3 nA/μm at <i>VG</i> = 2V. The subthreshold characteristics with a swing of 228 mV/dec and drain-induced barrier lowering of 288 mV/V are demonstrated.

Heterojunctions Formed on Si Substrate

Ge films were epitaxially grown on GaAs(100) substrates and Ga 0.88 In 0.12 As(100) virtual substrates using an ultrahigh vacuum/ chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an n + -Ge/p-GaAs diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source-drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device.

Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation

In this paper, we report Ge pand n-channel metal- oxide-semiconductor field-effect transistors (MOSFETs) with NiGe source/drain (S/D) with high performance and low leakage current. The forward/reverse current ratio of the NiGe/n-Ge and NiGe/p-Ge junctions were ~10⁵ and ~2 × 10⁴ at |V| = ±1 V, respectively. Interface state densities Dit of Al₂O₃/GeO₂/Ge stack is improved to be around 10¹²/eV^-1 cm² near the midgap after forming gas annealing; the gate-stack also shows excellent reliability under constant field stressing. Both p- and n-channel MOSFETs show sufficiently high I_ON/I_OFF ratio. High driving current of ~9 and ~4 μA/μm at |V_GS - V_T| = ±0.8 V and |V_DS| = ± V is obtained, respectively, for pand n-MOSFETs. Moreover, S/D series resistance R_SD of the p- and n-MOSFET is reduced by ~25% and ~42% as compared with that of the transistors with conventional p/n junctions.

Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High

In this paper, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I_ON/I_OFF ratio and good short channel effect control on the channel potential. The current ratio is of ~6×10³(ID) at V_DS=-0.1 V, V_GS=-3, and 0 V. The relatively low OFF-current is of 6 nA/ μm at V_DS=-0.1 V and V_GS=0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L_G=120 nm.

{\rm I}_{\rm ON}/{\rm I}_{\rm OFF}

For the first time, growth of high-quality Ge-rich Ge<inf>1−x</inf>Si<inf>x</inf> (0≤x≤0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge<inf>1−x</inf>Si<inf>x</inf> and a better thermal stability of the nickel germanide on Ge<inf>1−x</inf>Si<inf>x</inf> were observed. A higher rectifying ratio with a reduced diode leakage current in n⁺-Ge<inf>1−x</inf>Si<inf>x</inf>/p-Ge<inf>1−x</inf>Si<inf>x</inf> is compared with n⁺-Ge/p-Ge. These results indicate that it is suitable for Ge<inf>1−x</inf>Si<inf>x</inf> to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.

Ratio Ge FinFETs

We investigated the selective growth of germanium into nanoscale trenches on silicon substrates. These nanoscale trenches, the smallest size of which was 50 nm, were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. The formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. For the Ge grown in nanoscale Si areas (e.g., several tens of nanometers), the TDs were probably readily removed during cyclic thermal annealing predominantly because their gliding distance to the SiO 2 sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density.