Guarionex Morales

Process for reducing copper oxide during integrated circuit fabrication

Copper/low dielectric interconnect formation with reduced electromigration

Surface treatment of low-K SiOF to prevent metal interaction

Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal

High density plasma oxide gap filled patterned metal layers with improved electromigration resistance

Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure

Methods for characterizing and reducing adverse effects of texture of semiconductor films

Cobalt silicidation using tungsten nitride capping layer

Tungsten plug formation

Vacuum baked HSQ gap fill layer for high integrity borderless vias