Sarunya Bangsaruntip

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

We demonstrate the worlds first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs

Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that LEFF of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

Room-temperature carrier transport in high-performance short-channel Silicon nanowire MOSFETs

Room-temperature carrier transport in Si nanowire (NW) MOSFETs with gate lengths and diameters down to 25 and 8 nm, respectively, is analyzed. It is shown that in Si NWs, holes exhibit channel injection and thermal velocities, as high as the highest obtained for uniaxially strained planar Si-channel electrons, likely due to combination of strain and confinement.

Pulmonary toxicity, distribution, and clearance of intratracheally instilled silicon nanowires in rats

Silicon nanowires (Si NWs) are being manufactured for use as sensors and transistors for circuit applications. The goal was to assess pulmonary toxicity and fate of Si NW using an in vivo experimental model. Male Sprague-Dawley rats were intratracheally instilled with 10, 25, 50, 100, or 250 μg of Si NW (~20–30 nm diameter; ~2–15 μm length). Lung damage and the pulmonary distribution and clearance of Si NW were assessed at 1, 3, 7, 28, and 91 days after-treatment. Si NW treatment resulted in dose-dependent increases in lung injury and inflammation that resolved over time. At day 91 after treatment with the highest doses, lung collagen was increased. Approximately 70% of deposited Si NW was cleared by 28 days with most of the Si NW localized exclusively in macrophages. In conclusion, Si NW induced transient lung toxicity which may be associated with an early rapid particle clearance; however, persistence of Si NW over time related to dose or wire length may lead to increased collagen deposition in the lung.

Gate-all-around silicon nanowire MOSFETs and circuits

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.

Characterization of new aromatic polymers for 157-nm photoresist applications

There is currently tremendous interest in developing 157nm photoresists for imaging applications at 100nm and below. Due to the high VUV absorbance of the polymers used in 248 and 193 photoresists new materials are being investigated for applications at 157nm. In this report the characterization of a number of partially fluorinated polymers based on aromatic backbones will be described. Data on the absorbance, dissolution properties, solvent retention and acid diffusion characteristics of these systems will be presented.

Pattern transfer of directed self-assembly (DSA) patterns for CMOS device applications

We present a study on the optimization of etch transfer processes for circuit relevant patterning in the sub 30 nm pitch regime using directed self assembly (DSA) line-space patterning. This work is focused on issues that impact the patterning of thin silicon fins and gate stack materials. Plasma power, chuck temperature and end point strategy is discussed in terms of their effect on critical dimension (CD) control and pattern fidelity. A systematic study of post-plasma etch annealing processes shows that both CD and line edge roughness (LER) in crystalline Si features can be further reduced while maintaining a suitable geometry for scaled FinFET devices. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode and a SiN capping layer are also presented. We conclude with the presentation of a strategy for realizing circuit patterns from groups of DSA patterned fins. These combined results further establish the viability of DSA pattern generation as a potential method for CMOS integrated circuit patterning beyond the 10 nm node.

Contact engineering and channel doping for robust carbon nanotube NFETs

In this work, we present several strategies of making robust carbon nanotube (CNT) n-type field-effect transistors (NFETs). One approach uses low-work function metal contacts to enable electron injection into CNT for NFET operation while using pre-defined oxide trenches to protect the sidewalls of such easily oxidized contacts. The sidewall-protected NFETs are shown to be stable over several months. The contact length scaling study reveals a large contact resistance that increases rapidly as the contact size shrinks, probably due to the poor interface wetting. A thin Ti layer is shown to significantly enhance contact wetting on CNT and improve device performance. Another approach involves charge-transfer doping from layers deposited on top of CNT channel. Results from different doping layers and deposition conditions are presented and compared. For applications like CNT thin film transistors (TFTs, where transport is not limited by contacts), such channel doping techniques will be required to form NFETs.