H. Darabi

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Fully Integrated MIMO Multi-Band Direct-Conversion CMOS Transceiver for WLAN Applications (802.11n)

A single-chip multi-band direct-conversion CMOS MIMO transceiver (2 times 2) targeted for WLAN applications is presented. This transceiver is capable of satisfying the requirements of the Enhanced Wireless Consortium and achieves PHY rates of >270Mb/s. The receivers and transmitters achieve an EVM of better than -41 dB (0.9%) and -40dB (1.0%) operating in legacy g and a modes, respectively. From a 1.8V supply and with both cores operating, the chip draws 275mA in RX mode and 280mA in TX mode.

A 65nm CMOS quad-band SAW-less receiver for GSM/GPRS/EDGE

A quad-band 2.5G receiver integrates the front-end SAW filters, the LNA matching, as well as the RF baluns, achieving a typical sensitivity of close to −111dBm. Utilizing an arrangement of only four baseband capacitors and MOS switches driven by 4-phase 25% duty-cycle clocks, high-Q BPFs are realized to attenuate the 0dBm out-of-band blocker. The SAW-less receiver draws 55mA from the battery, and measures an out-of-band 1dB-compression of greater than +2dBm.

A tunable integrated duplexer with 50dB isolation in 40nm CMOS

Modern RF duplexers rely on frequency-selective filters for isolation. The stringent isolation requirements prohibit the integration of RF duplexers on silicon and particularly in CMOS technology. However, CMOS technology offers superior tuning and calibration capabilities supported by the integrated digital baseband. This work presents the first integrated duplexer in CMOS technology with an adequate performance for full-duplex cellular applications such as WCDMA and HSPA. The proposed implementation is based on electrical balance of a hybrid transformer rather than frequency selectivity which unfavorably requires high-Q elements.

A dual mode 802.11b/Bluetooth radio in 0.35/spl mu/m CMOS

A dual-mode CMOS 2.4GHz transceiver consumes 65mA in RX and 78mA in TX from a 3V supply. The receiver achieves a typical sensitivity of -88dBm at 11Mb/s for 802.11b, and -83dBm for Bluetooth mode. The receiver minimum IIP3 is -8dBm, and the transmitter delivers a nominal output power of 0dBm, with a power control range of 20dB in 2dB steps.

A quad-band GSM/GPRS/EDGE SoC in 65nm CMOS

A quad-band 2.5G SoC integrates all the RF, DSP, ARM, audio and other baseband processing functions into a single 65nm CMOS die. The radio draws a battery current of 49mA in the RX-mode, and 86mA in the GMSK TX-mode. The low-IF receiver achieves a sensitivity of −110dBm at the antenna, corresponding to a noise figure of 2.4dB at the device input. The 8PSK ±400kHz modulation mask is −64.1/62.7dBc for high/low bands, with an RMS EVM of 2.45/1.95%.

A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS

This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into a single CMOS chip. Compared to the published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves a superior receive and transmit performance, and yet has up to 2x lower receive power consumption, a key requirement in cellular applications.

An IF FSK demodulator for Bluetooth in 0.35 /spl mu/m CMOS

An FSK demodulator intended for use in Bluetooth is implemented in a 0.35 /spl mu/m CMOS process. The entire demodulator, integrated as a part of a low-IF receiver with 2 MHz intermediate frequency, consumes 3 mA from 2.7 V supply. The required signal-to-noise ratio (SNR) for 0.1% bit error rate (BER) is about 18 dB.

A fully integrated SoC for 802.11b in 0.18 /spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.

An analog GFSK modulator in 0.35 /spl mu/m CMOS [Bluetooth transmitter applications]

This paper describes an analog GFSK modulator, designed in 0.35 /spl mu/m CMOS, which consumes 600 /spl mu/A from a 3 V supply and realizes an analog implementation of the FM differential equation. The modulator operates at base-band and is integrated in a direct-conversion Bluetooth transmitter The circuit achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy.