Reinout Woltjer

Time dependence of p-MOSFET hot-carrier degradation measured and interpreted consistently over ten orders of magnitude

Hot-carrier degradation is measured and analyzed over ten orders of magnitude in time for three buried-channel p-MOSFET types with different oxide thicknesses. The effects of oxide charge and interface states are separated by using the charge-pumping technique. Two dominating effects are sufficient to account for the degradation. For worst case degradation, negative oxide charge and interface states are generated by electrons near the drain. This charge is distributed homogeneously over the oxide thickness and it attracts an inversion layer that extends the drain and reduces the effective transistor length logarithmically in time. Simultaneously, this inversion layer prevents substantial degradation related to the interface states, since it masks their effects. A simple model for the logarithmic time dependence is presented. At more negative gate voltages, holes cause interface states that reduce the transconductance with a power-law time dependence, comparable to the worst case n-MOSFET degradation. >

Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's

Hot-carrier degradation is mainly caused by negative oxide-charge generation in the present-day PMOSFETs. We present experimental evidence showing that two more degradation mechanisms are important in the case of deep-submicron PMOSFETs. Firstly, the generation of interface states is significant in the case of sub-half-micron PMOSFETs. It even limits the lifetime of surface-channel transistors. Secondly, the generation of positive oxide charge by holes influences the characteristics. The latter process has been established unambiguously for the first time in PMOSFETs. We measured the bias dependence, the length dependence, and the time dependence separately for all three microscopic degradation mechanisms. We calculated the influence of these three mechanisms on the transconductance degradation. Summation of the three effects yields an excellent description of the experimentally determined time dependence of PMOSFET degradation for many bias conditions and various transistor geometries with either nitrided or conventional gate oxide. >

A new monitor to predict hot-carrier damage of PMOS transistors

Damage due to hot-carrier degradation of PMOS transistors is analyzed in detail for various transistor types. The authors describe the worst-case degradation mechanism and propose a new damage monitor. The damage caused by hot-carrier degradation is well characterized by channel shortening normalized on oxide thickness. This new monitor may be used to predict the damage over a large factor (10/sup 5/) in time when the damage after a short time is measured. The electrical characteristics after hot-carrier degradation are shown to be fully determined when the channel shortening is predicted by the proposed method.<<ETX>>

Modeling of oxide-charge generation during hot-carrier degradation of PMOSFET's

Oxide-charge generation determines the lifetime for hot-carrier degradation of PMOSFETs. We present a model for the generation of oxide charge and its influences on transistor characteristics. Our model explains the logarithmic time dependence for the generation of oxide charge that is observed systematically for many PMOSFET types. This model is in accordance with an empirical prediction method for PMOSFET degradation that has been published earlier. Furthermore, a relation between the injected charge and the amount of degradation is presented. The paper ends with some applications. >

Positive oxide-charge generation during 0.25 /spl mu/m PMOSFET hot-carrier degradation

A new hot-carrier degradation mechanism becomes important in 0.25 /spl mu/m PMOSFETs. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge.<<ETX>>

N/sub 2/O nitrided gate dielectric technology for 0.25 mu m CMOS

A technology for thin N/sub 2/O nitrided gate oxide was developed for 0.25 mu m CMOS. A gate dielectric of 7.5 nm thickness was grown using a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900 degrees C, the second step is nitridation in pure N/sub 2/O at 950 degrees C. The use of lightly nitrided gate dielectrics improved the gate oxide quality and did not degrade the MOS device properties. Furthermore, boron diffusion through the thin dielectric of BF/sub 2/ doped poly gates was suppressed by N/sub 2/O nitridation.<<ETX>>

New hot-carrier degradation mechanisms in 0.25 /spl mu/m PMOSFETs

PMOSFET hot-carrier reliability is often proposed to he limited by negative oxide charge. We show that interface states determine the lifetime in deep submicron PMOSFETs. Clear evidence for additional positive oxide-charge generation is presented for the first time. The bias-length and time dependences are measured for all three degradation mechanisms. Combining these three mechanism describes the time dependence of PMOSFET degradation convincingly for many geometries at many bias conditions.<<ETX>>

The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors

An experimental study of hot carrier degradation and power supply voltage scaling of deep-submicron NMOS devices is presented. Devices were optimized for processes with design rule between 2 mu m and 0.17 mu m. Charge pumping measurements showed that the lifetime based on interface state generation in the devices was determined only by I/sub sub//I/sub d/ and the drain current. It did not depend on gate length, oxide thickness, and substrate doping. The lifetime (determined by shifts in the maximum linear transconductance) of the devices with minimum gate length of different processes fall on a single life in plots of tau *I/sub d/ versus I/sub sub//I/sub d/. This behavior can be explained by the impact of interface damage on the transistor parameters of these devices. Light emission spectra and device simulation showed that nonlocal carrier heating becomes important for devices from deep-submicron processes. As a result the power supply voltage is almost independent of design rule for the deep-submicron process (V/sub dd/<or=2.5 V).<<ETX>>

Oxide-charge generation during hot-carrier degradation of PMOSTs

A new model for oxide-charge generation in PMOSFETs is proposed and verified experimentally. It incorporates Coulomb repulsion and it takes the spatial distribution of the injection into account. It predicts the time dependencies of the gate current, oxide charge, threshold voltage and transconductance. Finally, an extension towards a two-step degradation mechanism is discussed.<<ETX>>

An industrial view on compact modeling

Compact modeling is an area that gets more and more mature. Collaborations and standardization efforts have emerged. In this paper we present some special requirements that are important when constructing physics-based compact models. We will substantiate our statements on two recent examples, an inductor model and a MOSFET model