H. H. Kim

Enhancement of data retention and write current scaling for sub-20nm STT-MRAM by utilizing dual interfaces for perpendicular magnetic anisotropy

We investigate the sub-20nm level scalability of STT-MRAM cells possessing perpendicular magnetization induced from the interface of free layer (FL) and MgO tunnel barrier. We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface. As thermal stability factor (Δ) varies as a function of MTJ dimension, MTJs with dual interfaces show Δ over 60 at 20nm node, while MTJs of single interface show Δ around 33. MTJs with dual interface also exhibit lower switching current per thermal stability (Ic/Δ), ~1/2 level of single interface MTJs.

130 nm-technology, 0.25 μm 2 , 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications

We have successfully demonstrated a world smallest 0.25 μm2 cell ITIC 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new FRAM cell is suitable for a mobile SoC (System-on-a-Chip) application. This is due to realization of four metal technology required for high-speed logic devices. As a result, the remanent polarization value of 32 μC/Cm2 was achieved after full integration and the sensing window was evaluated to 370 mV at 85degC, 1.3 V.

Highly manufacturable 1T1C 4 Mb FRAM with novel sensing scheme

A novel sensing scheme using a gate-oxide reference cell is developed for achieving high yield of 1T1C FRAM. The sensing scheme generates highly uniform and fatigue-free reference level, and thus provides a reliable sensing margin. A novel technology to evaluate charge distribution of all memory cells is used for identifying the root causes of bit failure which are most critical factor for yield loss. Using this technology, hydrogen damage and etching damage are found to be the major loss factors. By eliminating the etch-damage with wet treatment and by using robust hydrogen-barrier, a wide sensing window, /spl Delta/Qref=74 fC, was achieved for highly manufacturable FRAM.

A novel 1T1C capacitor structure for high density FRAM

In this paper, an etching damage-free 4 Mb ferroelectric random access memory (FRAM) integration technology was for the first time developed using ferroelectric (FE) hole capacitor structure. Since the PZT capacitors are not etched, no etching damage was generated in the novel capacitor structure. The etching process issue, which is one of most critical obstacles for scaling down FRAM device, is completely resolved by using this novel FE hole structure. Therefore, the novel integration technology strongly promises to provide a reliable scaling down of FRAM device beyond 0.25 /spl mu/m technology generation.

An endurance-free ferroelectric random access memory as a non-volatile RAM

We demonstrate endurance characteristics of a 1T1C, 64 Mb FRAM in a real-time operational situation. To explore endurance properties in address access time tAA of 100 ns, we establish a measurement set-up that covers asymmetric pulse-chains corresponding to D1- and D0-READ/RESTORE/WRITE over a frequency range from 1.0 to 7.7 MHz. What has been achieved is that endurance cycles approximate 5.9 times 1024 of cycle times in an operational condition of VDD = 2.0 V and 85degC in the developed 64 Mb FRAM. Donor concentration due to build-up of oxygen vacancy in a ferroelectric film has also been evaluated to 2.3 times 1020 cm-3 from I-V-t measurements.

Electrical properties of highly reliable 32 Mb FRAM with advanced capacitor technology

Highly reliable 32Mb FRAM was successfully developed by double annealing technique and CVD deposition technique. The optimized annealing method generates highly (111) oriented ferroelectric films, resulting in large remnant polarization. The CVD process provides strong interface between electrode and ferroelectric films, giving rise to minimal integration degradation and strong retention properties. After baking test at 150 /spl deg/C for 100hrs, a wide sensing window of 350 mV was achieved to guarantee strong retention properties for high density FRAM products.

Key Integration Technologies for Nanoscale FRAMs

We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise (1) etching technology to have less plasma damage; (2) stack technology for the preparation of robust ferroelectrics; (3) capping technology to encapsulate cell capacitors; and (4) vertical conjunction technology to connect cell capacitors to the plate-line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but to ensure sensing margin of 300 mV in opposite-state retention even after 1000 hours at 150degC.

A Highly Reliable FRAM (Ferroelectric Random Access Memory)

64 Mb FRAM with 1T1C (one-transistor and one-capacitor) cell architecture has progressed greatly for a robust level of reliability. Random-single-bits appeared from package-level tests are attributed mostly to extrinsic origins (e.g. interconnection failures) rather than intrinsic ones. The extrinsic failures can be linked to two activation energies: while one is 0.27 eV originated from oxygen-vacancy movements at the top interface and grain boundary in the ferroelectric films, the other is 0.86 eV caused by imperfection in either the top-electrode contact (TEC), or the bottom-electrode contact (BEC), or both, of the cell capacitor. As a result of applying novel schemes to remove the analyzed defectives, we have the FRAM with no bit failure up to 1000 hours over both high-temperature-operating-life (HTOL) and high-temperature-storage (HTS) tests

World Smallest 0.34/spl mu/m~ COB Cell 1T1C 64Mb FRAM with New Sensing Architecture and Highly Reliable MOCVD PZT Integration Technology

We have successfully demonstrated a 0.34mum2 COB cell 1T1C 64Mb FRAM at 150nm technology node. The minimum signal window between data 1 and data 0 of 64M bit cells was evaluated to 300mV at 85degC, 1.6V VDD. This wide signal window was achieved by introducing advanced anneal technology and optimized capacitor layout, from which the variation of individual cell charge was greatly improved, along with robust 2-D stack capacitor technologies such as 70nm thick MOCVD PZT technology with SRO electrode. In addition, a new reference cell scheme for 1T1C architecture, the multi-reference cell equalizing scheme (MRCE), greatly improved the variation of the reference cell signal for sufficient 1T1C sensing margin. As a result, no single bit failure was found in our 1T1C 64Mb FRAM after 500hour bake at 150degC

Integration and Electrical Properties of Novel Ferroelectric Capacitors for 0.25 µm 1 Transistor 1 Capacitor Ferroelectric Random Access Memory (1T1C FRAM)

Since the space margin between capacitors has been greatly reduced in 32 Mb high-density ferroelectric random access memory (FRAM) with a 0.25 µm design rule, considering the limitation of current etching technology, the stack height of ferroelectric capacitors should be minimized for stable node separation. In this paper, novel capacitors with a total thickness of 4000 A were prepared using a seeding layer, low temperature processing, and optimal top electrode annealing. The 1000 A Pb(Zr1-xTix)O3 (PZT) films showed excellent structural and ferroelectric properties such as strong (111) orientation and large remanent polarization of 40 µC/cm2. The low stack capacitors were then implemented into 0.6 µm and prototype 0.25 µm FRAM. Compared to a conventional capacitor stack, the ferroelectric capacitors exhibited adequate sensing margin of 250 fC, thus giving rise to a fully working die of 4 Mb FRAM. Therefore, it was clearly demonstrated that the novel capacitors can enable the realization of a high-density 32 Mb FRAM device with a 0.25 µm design rule.