Dong-Jin Jung

Integration and electrical properties of diffusion barrier for high density ferroelectric memory

A reliable Ir diffusion barrier was prepared on polysilicon plugged substrate with a contact size of 0.6 μm. Using a Ti adhesion layer and stress-relief process, it was possible to integrate the Ir barrier into a high density 4 Mb ferroelectric random access memory device. After heat treating sol-gel derived Pb(Zr1−xTix)O3 (PZT) films at 700 °C, the Ir barrier contact displayed an ohmic behavior and showed a low resistance of 130 Ω per contact in 1k serial contact array. The PZT films on Pt/IrO2/Ir poly-plugged substrate exhibited excellent ferroelectric properties such as remnant polarization and coercive voltage of 25 μC/cm2 and 1.15 V, respectively. Auger depth profile and transmission electron microscopy analyses confirmed that no appreciable oxidation was formed between the Ir barrier and the polysilicon plug.

A 0.25 /spl mu/m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme

A nonvolatile 32 Mb ferroelectric random-access memory with 0.25 /spl mu/m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty.

Switching kinetics in nanoferroelectrics

We have measured the switching in ferroelectric capacitors of lead zirconate titanate (PZT) over three orders of magnitude in lateral area, from A = 166 to 0.19 µm2 (the latter being the size of the smallest ferroelectric random access memory (FRAM) cells in production), and over three orders of magnitude in ramp rate of applied voltage (d E(t)/d t = 107–1010 V cm−1 s−1). In accord with the model of Scott (1998 Ferroelectr. Rev. 1 1), the submicron cells follow a different dependence to the larger cells: for A\gg 1~\micmu {\mathrm {m}}^{2} , the data fit a theory due to Landauer et al (the LYD model), which neglects nucleation; whereas the nanoscale devices satisfy the functional dependence predicted by Pulvari and Kuebler (the PK model), albeit with a modified coefficient. This crossover behaviour has implications for Gbit FRAM device performance at high speed. Fringing field effects measured agree with a simple model from Feynman.

Electrical properties of highly reliable plug buffer layer for high-density ferroelectric memory

A CoSi2 buffer layer was prepared in polycrystalline silicon (polysilicon) plug for preventing an undesired microvoid between the polysilicon plug and Ir/Ti diffusion barrier. Since the microvoid generates random function fail, resulting in low wafer yield of a 4 Mb ferroelectric random access memory device, we developed the thermally stable CoSi2 buffer layer for eliminating the random single bit fails. The ferroelectric capacitors using the CoSi2 buffer layer showed a low contact resistance of 96 Ω per contact in 1k serial contact array with contact size of 0.6 μm, and also exhibited great ferroelectric properties such as remnant polarization and coercive voltage of 20 μC/cm2 and 1.2 V, respectively. Scanning electron microscopy analyses confirmed that no microvoid was formed between the interface between the Ir/Ti barrier layer and the CoSi2 buffer layer.

130 nm-technology, 0.25 μm 2 , 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications

We have successfully demonstrated a world smallest 0.25 μm2 cell ITIC 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new FRAM cell is suitable for a mobile SoC (System-on-a-Chip) application. This is due to realization of four metal technology required for high-speed logic devices. As a result, the remanent polarization value of 32 μC/Cm2 was achieved after full integration and the sensing window was evaluated to 370 mV at 85degC, 1.3 V.

A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs

Recently, ferroelectric random access memory has drawn a great deal of attention due to inherent properties such as nonvolatility, long retention time, high endurance, fast access time, small cell size compared to DRAM cell size in principle, and strong resistance to /spl alpha/-particle and cosmic ray irradiation. None of the available commercial memories meet all of the properties of the ferroelectric memory. Although ferroelectric memory has inherent good properties, full utilization of these properties has not yet been realized. Commercially available products are limited to low densities. The commercially available ferroelectric memory uses a 2T2C (two transistor-two capacitor) structure with single level metal instead of a 1T1C (one transistor-one capacitor) structure with multiple metal layers which is believed to be essential for mega-bit or giga-bit density memory. In this paper, an integration technology for high performance and high density FRAMs is developed using a 1T1C robust capacitor in a COB (capacitor over bit line) structure with triple metallization processes. The technology developed in this paper is evaluated with an experimental 4 Mb FRAM, which is the highest FRAM density developed to date.

Novel integration technologies for highly manufacturable 32 Mb FRAM

Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.

A 1T/1C Ferrodectric RAM Using A Double-level Metal Process For Highly Scalable Nonvolatile Memory

A double-level metal, one-poly, 1T/lC 64k ferroelectric RAM has been successfully fabricated with 1.2~ conventional CMOS technology. By realizing aluminum bit line, aluminum plate line in the doublelevel metal process without degrading Pt/PZT/Pt ferroelectric capacitor and by adopting lT/lC cell archtecture, lOOns data access time was obtained at Vcc=S.OV which is faster by 40% than the commercialized 2T/2C FRAM with a single-level metal. A proper annealing processes was proved to be the key for the recovery of the ferroelectric capacitor degradation caused by the double-level metal integration process.

Highly manufacturable 1T1C 4 Mb FRAM with novel sensing scheme

A novel sensing scheme using a gate-oxide reference cell is developed for achieving high yield of 1T1C FRAM. The sensing scheme generates highly uniform and fatigue-free reference level, and thus provides a reliable sensing margin. A novel technology to evaluate charge distribution of all memory cells is used for identifying the root causes of bit failure which are most critical factor for yield loss. Using this technology, hydrogen damage and etching damage are found to be the major loss factors. By eliminating the etch-damage with wet treatment and by using robust hydrogen-barrier, a wide sensing window, /spl Delta/Qref=74 fC, was achieved for highly manufacturable FRAM.

A novel 1T1C capacitor structure for high density FRAM

In this paper, an etching damage-free 4 Mb ferroelectric random access memory (FRAM) integration technology was for the first time developed using ferroelectric (FE) hole capacitor structure. Since the PZT capacitors are not etched, no etching damage was generated in the novel capacitor structure. The etching process issue, which is one of most critical obstacles for scaling down FRAM device, is completely resolved by using this novel FE hole structure. Therefore, the novel integration technology strongly promises to provide a reliable scaling down of FRAM device beyond 0.25 /spl mu/m technology generation.