D. Y. Choi

130 nm-technology, 0.25 μm 2 , 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications

We have successfully demonstrated a world smallest 0.25 μm2 cell ITIC 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new FRAM cell is suitable for a mobile SoC (System-on-a-Chip) application. This is due to realization of four metal technology required for high-speed logic devices. As a result, the remanent polarization value of 32 μC/Cm2 was achieved after full integration and the sensing window was evaluated to 370 mV at 85degC, 1.3 V.

An endurance-free ferroelectric random access memory as a non-volatile RAM

We demonstrate endurance characteristics of a 1T1C, 64 Mb FRAM in a real-time operational situation. To explore endurance properties in address access time tAA of 100 ns, we establish a measurement set-up that covers asymmetric pulse-chains corresponding to D1- and D0-READ/RESTORE/WRITE over a frequency range from 1.0 to 7.7 MHz. What has been achieved is that endurance cycles approximate 5.9 times 1024 of cycle times in an operational condition of VDD = 2.0 V and 85degC in the developed 64 Mb FRAM. Donor concentration due to build-up of oxygen vacancy in a ferroelectric film has also been evaluated to 2.3 times 1020 cm-3 from I-V-t measurements.

Key Integration Technologies for Nanoscale FRAMs

We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise (1) etching technology to have less plasma damage; (2) stack technology for the preparation of robust ferroelectrics; (3) capping technology to encapsulate cell capacitors; and (4) vertical conjunction technology to connect cell capacitors to the plate-line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but to ensure sensing margin of 300 mV in opposite-state retention even after 1000 hours at 150degC.

A Highly Reliable FRAM (Ferroelectric Random Access Memory)

64 Mb FRAM with 1T1C (one-transistor and one-capacitor) cell architecture has progressed greatly for a robust level of reliability. Random-single-bits appeared from package-level tests are attributed mostly to extrinsic origins (e.g. interconnection failures) rather than intrinsic ones. The extrinsic failures can be linked to two activation energies: while one is 0.27 eV originated from oxygen-vacancy movements at the top interface and grain boundary in the ferroelectric films, the other is 0.86 eV caused by imperfection in either the top-electrode contact (TEC), or the bottom-electrode contact (BEC), or both, of the cell capacitor. As a result of applying novel schemes to remove the analyzed defectives, we have the FRAM with no bit failure up to 1000 hours over both high-temperature-operating-life (HTOL) and high-temperature-storage (HTS) tests

Quality assured mass productive 1.6V operational 0.18 /spl mu/m 1T1C FRAM embedded smart card with advanced integration technologies against defectives

We have made great progress for mass production of a highly reliable 1.6V, 0.18 mum 1T1C FRAM embedded smart card. For mass production, our device has to pass standard qualification tests on the package level. These contain the infant life test (ILT), the high temperature operating life (HTOL), the endurance and the high temperature storage (HTS) test. Problems in the PZT capacitor integration scheme led to single bit fails during the standard ILT, HTOL and HTS tests. The causes are broken EBL and TE/PZT interface damage, which were removed by the modification of top electrode deposition and capacitor etching processes and by a new capping oxide deposition scheme

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.

A Novel Encapsulation Technology for Mass-Productive 150 nm, 64-Mb, 1T1C FRAM

In order to realize a cost-effective high density FRAM product over 64-Mb, it is inevitable to develop technologies for a small cell and large wafer size without degradation during full integration. We have successfully demonstrated a fully functional 0.16 mum2 capacitor size, 64-Mb, 1T1C FRAM on an 8-inch wafer by introducing new integration technologies at 150 nm technology node. One of the key technologies is the use of novel capping layer, i.e. Al2O3, which prevents the capacitor from the degradation caused by following integration process. It was found that novel capping Al2O3 layer was very effective to block chronic hydrogen diffusion, and depending on the wafer size, the effective capping layer condition is changed. By introducing a novel capping layer of Al2O3 and optimizing its process conditions, the fully integrated ferroelectric capacitor for the 150 nm, 64-Mb, 1T1C FRAM on the 8-inch Si-substrate shows good ferroelectric properties such as a polarization value of 33 muC/cm2 with an uniform distribution of sigma = 1.27, and the sensing window of 300 mV at 85degC.

Robust Two-Dimensional Stack Capacitor Technologies for 64 Mbit One-Transistor–One-Capacitor Ferroelectric Random Access Memory

It is very important to develop capacitor module technologies such as robust Pb(ZrxTi1-x)O3 (PZT) film technology at nm scaled PZT thickness and damage minimized ferroelectric capacitor etching technology are crucial for the success of high density one-transistor–one-capacitor (1T1C) ferroelectric random access memory (FRAM). We resolved this issue from the change of the capacitor etching system and optimization of the PZT/SrRuO3 (SRO) deposition process. As a result, we realized a highly reliable sensing window for 64 Mbit 1T1C FRAM that were realized by novel technologies such as robust MOCVD PZT deposition technologies, optimized SRO electrode and damage minimized ferroelectric capacitor etching technologies.

A methodology to characterize device-level endurance in 1T1C (1-transistor and 1-capacitor) FRAM

We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Data 1 (D1) and Data 0 (D0) READ/RESTORE over a frequency range from 1.0 to 7.7 MHz. The cycle-to-failure of 5.9 × 1024 cycles in an operational condition of 7.7 MHz and 85 °C, has been obtained from extrapolation to VDD = 2.0 V in a voltage acceleration. We compare testing results with those of D1¿D0 populations of bit-line potential.

Hydrogen-and-Stress-Induced de-lamination in an IrO 2 Layer of FRAMs

FRAMs (ferroelectric random access memories) draw much attention as a NVRAM (non-volatile random access memory) device due to the fact that they have ideal memory properties such as a fast READ/WRITE speed (200 MB/s in bandwidth), low power consumption (~μA in stand-by current), and reasonable memory density (several ten megabit or more)[1]. To meet the requirement of customers’ need in a package level, several acceleration tests such as HTOL (high temperature operational life) test and HTS (high temperature storage) test, has long been applied to ensure a device lifetime. During the high temperature tests, in our case, a few defective points have appeared and localized in specific cell arrays. The main cause of the imperfection turns out to be physical de-lamination of the IrO2 layer in vertical conjunction to pulsed plate-line, so-called here ATE, additional-top-electrode (see Fig.1) In one hand, IrO2 can, in general, be readily affected by many ambient conditions such as temperature, pressure, and hydrogen or its related materials[2-4]. On the other, reduction of the IrO2 layer often become metallic Ir, stress value of which is approximately one order of magnitude larger than that of conventional metals. Thus, in this paper, we present how heat treatments of BEOL (backend of line) integration influence IrO2 to be reduced. Also, we simulate stress distribution in cell arrays depending on how many dummy cells have been taken into account. Along with this, we suggest a schematic model to describe the possible paths of hydrogen involvement during the BEOL integration.