Y. M. Kang

Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologies

We developed FRAM embedded smartcard in which FRAM replace EEPROM and SRAM to improve the read/write cycle time and endurance of data memories in smartcard. Highly reliable sensing window for FRAM embedded smartcard was achieved by advanced integration technologies such as novel capacitor technology, multi-level encapsulating barrier layer (EBL) technology, and optimal inter-metallic dielectrics (IMD) technology.

130 nm-technology, 0.25 μm 2 , 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications

We have successfully demonstrated a world smallest 0.25 μm2 cell ITIC 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new FRAM cell is suitable for a mobile SoC (System-on-a-Chip) application. This is due to realization of four metal technology required for high-speed logic devices. As a result, the remanent polarization value of 32 μC/Cm2 was achieved after full integration and the sensing window was evaluated to 370 mV at 85degC, 1.3 V.

An endurance-free ferroelectric random access memory as a non-volatile RAM

We demonstrate endurance characteristics of a 1T1C, 64 Mb FRAM in a real-time operational situation. To explore endurance properties in address access time tAA of 100 ns, we establish a measurement set-up that covers asymmetric pulse-chains corresponding to D1- and D0-READ/RESTORE/WRITE over a frequency range from 1.0 to 7.7 MHz. What has been achieved is that endurance cycles approximate 5.9 times 1024 of cycle times in an operational condition of VDD = 2.0 V and 85degC in the developed 64 Mb FRAM. Donor concentration due to build-up of oxygen vacancy in a ferroelectric film has also been evaluated to 2.3 times 1020 cm-3 from I-V-t measurements.

Electrical properties of highly reliable 32 Mb FRAM with advanced capacitor technology

Highly reliable 32Mb FRAM was successfully developed by double annealing technique and CVD deposition technique. The optimized annealing method generates highly (111) oriented ferroelectric films, resulting in large remnant polarization. The CVD process provides strong interface between electrode and ferroelectric films, giving rise to minimal integration degradation and strong retention properties. After baking test at 150 /spl deg/C for 100hrs, a wide sensing window of 350 mV was achieved to guarantee strong retention properties for high density FRAM products.

Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application

Multi-bit vertical structure NAND (VsNAND) flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10 nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and word line patterning. VsNAND flash array cells with TANOS (TaN/Al2O3/SiN/SiOx/Si) charge trap structure show possibilities of acceptable program/erase properties and cell Vth distribution characteristics for multi-level NAND flash application.

Key Integration Technologies for Nanoscale FRAMs

We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (metal-insulator-metal) capacitors. The key integration technologies in ferroelectric random access memory (FRAM) comprise (1) etching technology to have less plasma damage; (2) stack technology for the preparation of robust ferroelectrics; (3) capping technology to encapsulate cell capacitors; and (4) vertical conjunction technology to connect cell capacitors to the plate-line. What has been achieved from these novel approaches is not only to have a peak-to-peak value of 675 mV in bit-line potential but to ensure sensing margin of 300 mV in opposite-state retention even after 1000 hours at 150degC.

A Highly Reliable FRAM (Ferroelectric Random Access Memory)

64 Mb FRAM with 1T1C (one-transistor and one-capacitor) cell architecture has progressed greatly for a robust level of reliability. Random-single-bits appeared from package-level tests are attributed mostly to extrinsic origins (e.g. interconnection failures) rather than intrinsic ones. The extrinsic failures can be linked to two activation energies: while one is 0.27 eV originated from oxygen-vacancy movements at the top interface and grain boundary in the ferroelectric films, the other is 0.86 eV caused by imperfection in either the top-electrode contact (TEC), or the bottom-electrode contact (BEC), or both, of the cell capacitor. As a result of applying novel schemes to remove the analyzed defectives, we have the FRAM with no bit failure up to 1000 hours over both high-temperature-operating-life (HTOL) and high-temperature-storage (HTS) tests

Improvement in Reliability of 0.25 μ m 15F2 FRAM Using Novel MOCVD PZT Technology

We report on the measurements of reliability of 0.25 μ m 15F2 cell FRAM using novel MOCVD PZT technology. The MOCVD PZT capacitors were prepared using a pre-purging process and successfully integrated into the 32 Mb FRAM process with double EBL technology and optimal ILD/IMD scheme. After full integration, the 0.44 μ m2 MOCVD PZT capacitors with a 2Pr value of 35 μ C/cm2 at an applied voltage of 2.7 V show superior retention properties. The MOCVD PZT cells have large sensing windows of 420 mV at an operation voltage of 2.7 V. The sensing windows show only a slight decrease during 100 hours of baking at a temperature of 150°C, after which not a single cells is observed to fail. Therefore, it is clearly demonstrated that using the novel MOCVD PZT capacitors, high reliability of 0.25 μ m 15 F2 cell FRAM can be achieved.

Quality assured mass productive 1.6V operational 0.18 /spl mu/m 1T1C FRAM embedded smart card with advanced integration technologies against defectives

We have made great progress for mass production of a highly reliable 1.6V, 0.18 mum 1T1C FRAM embedded smart card. For mass production, our device has to pass standard qualification tests on the package level. These contain the infant life test (ILT), the high temperature operating life (HTOL), the endurance and the high temperature storage (HTS) test. Problems in the PZT capacitor integration scheme led to single bit fails during the standard ILT, HTOL and HTS tests. The causes are broken EBL and TE/PZT interface damage, which were removed by the modification of top electrode deposition and capacitor etching processes and by a new capping oxide deposition scheme

The challenges and directions for the mass-production of highly-reliable, high-density 1T1C FRAM

The directions to overcome the challenges, which we meet in the mass-production of highly-reliable high-density 1T/1C FRAM, are suggested. Controlling of the wide variations of individual cell signals and the exclusion of the weak cells with tailed cell signals will provide enough sensing signal margin, which is crucial for the safe and reliable operation of 1T/1C FRAM, and are the two key factors for the success of the mass-production of highly-reliable and high-density 1T/1C FRAM. The variations of cell to cell signals have been greatly reduced by improving process uniformity around cells and minimizing the integration-induced degradation of ferroelectric capacitor. The complete screening of weak cells with tailed sensing signals have been achieved by the introduction of the cell test with an external reference voltage. The 64 Mb experimental FRAM with the new processes and the novel test scheme has showed large sensing margins of ~200mV and excellent reliability properties.