Tewook Bang

Vertically Integrated Multiple Nanowire Field Effect Transistor

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.

A Vertically Integrated Junctionless Nanowire Transistor

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.

Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced From Hot-Carrier Injection

Device degradation induced by hot-carrier injection was repaired by electrical annealing using Joule heat through a built-in heater in a gate. The concentrated high temperature anneals the gate oxide locally and the degraded device parameters are recovered or further enhanced within a short time of 1 ms. Selecting a proper range of repair voltage is very important to maximize the annealing effects and minimize the extra damages caused by excessive high temperature. The repairing voltage is related to the resistance of the poly-Si gate according to the device scaling.

Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al2O3, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔVth) was 0 V even after a PBS time (tstress) of 3000 s under a gate voltage (VG) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔVth value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔVth values resulting from PBS quantitatively, the average oxide charge trap density (NT) in the GI and its spatial distribution were i...

Investigation of Low-Frequency Noise in Nonvolatile Memory Composed of a Gate- All-Around Junctionless Nanowire FET

Low-frequency noise (LFN) behaviors, characterized with an SONOS-based gate-all-around junctionless nanowire (JLNW), are investigated to determine the suitability of this type of NW as a memory cell structure. LFN exhibits a 1/f-shape and is described by a carrier number fluctuation noise model. It is found that the proposed device structure shows a low level of device-to-device variation and high immunity against Fowler-Nordheim tunneling stress. Due to the centered conduction path in the JLNW device, the impact of correlated mobility fluctuations on the LFN is insignificant. The trapped charge in the nitride layer of the Silicon(Poly-Si)-oxide(SiO2)-nitride(SiNx)-oxide(SiO2)-silicon(Single-crystalline) (SONOS) device also negligibly influences the LFN. The NW width-dependence is clarified in terms of the effects of the oxide trap density and source/drain series resistance under a fresh and a programmed state.

Electrothermal Annealing (ETA) Method to Enhance the Electrical Performance of Amorphous-Oxide-Semiconductor (AOS) Thin-Film Transistors (TFTs)

An electro-thermal annealing (ETA) method, which uses an electrical pulse of less than 100 ns, was developed to improve the electrical performance of array-level amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). The practicality of the ETA method was experimentally demonstrated with transparent amorphous In-Ga-Zn-O (a-IGZO) TFTs. The overall electrical performance metrics were boosted by the proposed method: up to 205% for the trans-conductance (gm), 158% for the linear current (Ilinear), and 206% for the subthreshold swing (SS). The performance enhancement were interpreted by X-ray photoelectron microscopy (XPS), showing a reduction of oxygen vacancies in a-IGZO after the ETA. Furthermore, by virtue of the extremely short operation time (80 ns) of ETA, which neither provokes a delay of the mandatory TFTs operation such as addressing operation for the display refresh nor demands extra physical treatment, the semipermanent use of displays can be realized.

Low-Frequency Noise Characteristics in SONOS Flash Memory With Vertically Stacked Nanowire FETs

Low-frequency (LF) noise in a vertically stacked nanowire (VS-NW) memory device, which is based on the silicon-oxide-nitride-oxide-silicon (SONOS) configuration is characterized in two different operational modes, an inversion-mode and a junctionless-mode (JM). The LF noise showed 1/f -shape behavior regardless of the operational mode and followed the carrier number fluctuation model. With regard to the device-to-device variation and quality degradation of the LF noise after iterative program/erase operations, the five-story JM SONOS memory showed comparatively high immunity arising from its inherent bulk conduction and no-junction feature. Despite the harsh fabrication condition used to construct five-story VS-NW, even the five-story JM SONOS memory exhibited LF noise characteristics comparable to those of one-story JM SONOS memory. Thus, the five-story JM SONOS memory is attractive due to its high-performance capabilities and good scalability.

Optimization of the intrinsic length of a PIN diode for a reconfigurable antenna

Through the characterization of a fabricated PIN diode with the aid of a simulation, a structural guideline for a reconfigurable antenna is developed. By comparing the conductivity with the equivalently normalized power, an optimal intrinsic channel length is determined. Simulation data show that a high carrier concentration is sustained along both the vertical and lateral directions in the intrinsic region. Due to the simple fabrication process and the controllability of the exposed channel region as well as the high carrier concentration with good uniformity, the proposed PIN diode is a viable candidate for a future antenna.

A Novel Technique for Curing Hot-Carrier-Induced Damage by Utilizing the Forward Current of the PN-Junction in a MOSFET

The hot-carrier-induced damage of a gate dielectric was cured with Joule heat generated by the forward current of the p-n junction between the body and drain, for the first time. The effective recovery voltage and pulse timewere optimized to cure the gate dielectricdamage produced by hot-carrier injection. Moreover, iterative damage and cyclic curing were experimentally demonstrated. Throughlow-frequency noise analyses, the degradationand recovery were verified by identifying trap density along the depth of the gate dielectric. Furthermore, this proposed method produced nearly the same recovery characteristics through source-to-body junction current in a short-channel device.