Jae Hur

Nature-Replicated Nano-in-Micro Structures for Triboelectric Energy Harvesting

Triboelectric nanogenerators with nature-replicated interface structures are presented. Effective contact areas of the triboelectric surfaces are largely enhanced because of the densely packed nano-in-micro hierarchical structures in nature. The enlarged contact area causes stronger triboelectric charge density, which results in output power increment. The interface engineering also allows the improved humidity resistance, which is an important parameter for the stable energy harvesting.

Vertically Integrated Multiple Nanowire Field Effect Transistor

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Comprehensive Analysis of Gate-Induced Drain Leakage in Vertically Stacked Nanowire FETs: Inversion-Mode Versus Junctionless Mode

A comprehensive analysis of the gate-induced drain leakage (GIDL) current of vertically stacked nanowire (VS-NW) FETs was carried out. In particular, two different operational modes of the VS-NW, an inversion mode (IM) and a junctionless mode (JM), were compared. The GIDL current of the JM-FET was considerably smaller than that of the IM-FET, and the reason for the difference was consequently determined by numerical simulations. It was found that the source of the difference between the IM-FET and JM-FET was the difference in source/drain (S/D) doping concentration, where the depletion width becomes the tunneling width, considering a long extension length at the S/D regions. The experimental results showed that the GIDL current of the NW FET was significantly controlled by longitudinal band-to-band tunneling (BTBT), rather than the transverse BTBT, as had been reported in the previous literature.

A Vertically Integrated Junctionless Nanowire Transistor

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.

Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor.

Three-dimensional (3-D) fin-structured carbon nanotube field-effect transistors (CNT-FETs) with purified 99.9% semiconducting CNTs were demonstrated on a large scale 8 in. silicon wafer. The fabricated 3-D CNT-FETs take advantage of the 3-D geometry and exhibit enhanced electrostatic gate controllability and superior charge transport. A trigated structure surrounding the randomly networked single-walled CNT channel was formed on a fin-like 3-D silicon frame, and as a result, the effective packing density increased to almost 600 CNTs/μm. Additionally, highly sensitive controllability of the threshold voltage (VTH) was achieved using a thin back gate oxide in the same silicon frame to control power consumption and enhance performance. Our results are expected to broaden the design margin of CNT-based circuit architectures for versatile applications. The proposed 3-D CNT-FETs can potentially provide a desirable alternative to silicon based nanoelectronics and a blueprint for furthering the practical use of emerging low-dimensional materials other than CNTs.

Investigation of Low-Frequency Noise in Nonvolatile Memory Composed of a Gate- All-Around Junctionless Nanowire FET

Low-frequency noise (LFN) behaviors, characterized with an SONOS-based gate-all-around junctionless nanowire (JLNW), are investigated to determine the suitability of this type of NW as a memory cell structure. LFN exhibits a 1/f-shape and is described by a carrier number fluctuation noise model. It is found that the proposed device structure shows a low level of device-to-device variation and high immunity against Fowler-Nordheim tunneling stress. Due to the centered conduction path in the JLNW device, the impact of correlated mobility fluctuations on the LFN is insignificant. The trapped charge in the nitride layer of the Silicon(Poly-Si)-oxide(SiO2)-nitride(SiNx)-oxide(SiO2)-silicon(Single-crystalline) (SONOS) device also negligibly influences the LFN. The NW width-dependence is clarified in terms of the effects of the oxide trap density and source/drain series resistance under a fresh and a programmed state.

A Core Compact Model for Multiple-Gate Junctionless FETs

A core model for multiple-gate junctionless FETs (Mug-JL-FETs) is proposed. The derived charge model is obtained via assumptions of simple potential profile for different types of Mug-JL-FETs. It was found that the linear potential approach is not accurate enough for a double-gate (DG) JL-FET, whereas it was reasonably precise for a DG inversion-mode FET. This discrepancy arises from their different operating mechanisms. Thus, the parabolic potential assumption, which is intuitively close to an actual potential profile in the Mug-FETs, was applied. As a consequence, two different formulas of the charge model in terms of depletion charges, gate capacitance, and capacitance inside the channel were found: one for a tetragonal shape of a cross-sectional channel based on a Cartesian coordinate and the other for a circular shape of a cross-sectional channel based on a cylindrical coordinate. Moreover, the proposed approach was applied for a realistically shaped channel, which is close to elliptic geometry, with a circular profile at the top and bottom parts of the channel and a rectangular profile at the center part of the channel. By applying the decoupling method reported previously, a drain current model, which is extended from the above-mentioned charge model, was also obtained.

A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poissons equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage (VT) equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of VT shows good agreement with the simulation results down to a channel length <;20 nm. The variability of VT is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated.

Ultra-Fast Erase Method of SONOS Flash Memory by Instantaneous Thermal Excitation

An ultra-fast erasing process that acts within 200 ns is demonstrated in a junctionless gate-all-around nanowire silicon-oxide-nitride-oxide-silicon device. Rapid erasing is enabled with the use of instantaneous thermal excitation (TE) through a double-ended gate structure. Charges inside the silicon nitride layer are de-trapped by Joule heating. Moreover, an in-situ self-annealing effect accompanied by the TE erase method is achieved; hence, both the tunnel oxide quality and the retention characteristics are less degraded compared with the conventional Fowler-Nordheim erase method.

Optimization of the intrinsic length of a PIN diode for a reconfigurable antenna

Through the characterization of a fabricated PIN diode with the aid of a simulation, a structural guideline for a reconfigurable antenna is developed. By comparing the conductivity with the equivalently normalized power, an optimal intrinsic channel length is determined. Simulation data show that a high carrier concentration is sustained along both the vertical and lateral directions in the intrinsic region. Due to the simple fabrication process and the controllability of the exposed channel region as well as the high carrier concentration with good uniformity, the proposed PIN diode is a viable candidate for a future antenna.