Haijun Lou

A Junctionless Nanowire Transistor With a Dual-Material Gate

A dual-material-gate junctionless nanowire transistor (DMG-JNT) is proposed in this paper. Its characteristic is demonstrated and compared with a generic single-material-gate JNT using 3-D numerical simulations. The results show that the DMG-JNT has a number of desirable features, such as high ON-state current, a large ON/OFF current ratio, improved transconductance Gm, high unity-gain frequency fT, high maximum oscillation frequency fMAX, and reduced drain-induced barrier lowering. The effects of different control gate ratios Ra and varied work-function differences between the two gates are studied. Finally, the optimization of Ra and the work-function difference for the proposed DMG-JNT is presented.

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

This letter describes the formation of one-time-programmable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm2 . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.

Uniaxial Strain Effects on Electron Ballistic Transport in Gate-All-Around Silicon Nanowire MOSFETs

Uniaxial strain effects on electron ballistic transport in extremely scaled gate-all-around nanowire MOSFETs with both [100] and [110] orientations are investigated in this paper. Band structures of nanowires without and with strain are calculated using the empirical sp3d5s* tight-binding model. The top-of-the-barrier model is utilized to simulate the electron ballistic transport. It is found that uniaxial [110] strain reduces the electron transport mass, but its effect gradually decreases and becomes insignificant when the dimension of the nanowire is scaled. In addition to existing band splitting caused by quantum confinement, [100] and [110] tensile strains induce further band splitting. Hence, the impact of the strain effects depends on whether the nanowire operates in the nondegenerated or degenerated mode. Simulation results show that uniaxial strain effects are more significant in [110] nanowires. The impact of surface orientation can still be observed even in deeply scaled nanowires.

A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, an analytical potential-based model in the subthreshold regime for short-channel junctionless cylindrical surrounding-gate MOSFETs is proposed as the source/drain depletion effect considered. The threshold voltage (Vth), subthreshold slope, and drain-induced barrier lowering are also correspondingly derived, which give explicit explanations of the short-channel effects on junctionless MOSFETs in the subthreshold regime. The compact model is verified by the numerical simulation, and the results match well.

Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs

In this paper, a SPICE compatible analytical surface-potential-based model for junctionless symmetric double-gate (JLDG) MOSFETs is described. By using the gradual-channel-approximation, the 1-D Poissons equation is solved to obtain the surface and central potential in the JLDG MOSFET for long channel case. A continuous drain current model with smooth transitions from fully depleted region to partially depleted and accumulation regions is then derived from the Pao-Sahs dual integral as a function of the surface and central potential at the source and drain terminals. The model is verified and validated by numerical simulations over a wide range of doping concentrations and device geometries. The model has been implemented in a circuit simulator and used to simulate some circuit building blocks without any convergent problem.

Suppression of tunneling leakage current in junctionless nanowire transistors

In this paper, the characteristics of tunneling leakage current for the dual-material gate junctionless nanowire transistor (DMG-JNT) are investigated by three-dimensional numerical simulations and compared with conventional junctionless nanowire transistor (JNT). The suppression of the tunneling leakage current on the JNT by introducing an energy band step with the DMG structure is verified and presented for the first time. The effects of channel length on the DMG-JNT and the JNT are also studied. Results showed that the tunneling leakage current of the DMG-JNT is two orders smaller than that of the JNT, and further, the DMG-JNT exhibits superior scaling capability. Two key design parameters of the DMG-JNT, control gate ratio (Ra) and work function difference (δW), have been optimized and the optimal ranges of Ra and δW are pointed out.

A Short Channel Double-Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect

A new model to capture the physics of short channel double-gate junctionless transistor (DGJT) has been developed. By solving the 2-D Poissons equation, the channel potential solution is obtained for both the physical channel and the dynamic channel extension to the source and drain. This dynamic change in channel boundary in DGJT has a strong impact on the performance of junctionless transistor, especially at reduced channel length. Based on the channel potential solution, a smooth and continuous drain current model is derived from Pao-Sahs dual integral. This model is valid for all operation modes, including full depletion, partial depletion, and accumulation. Extensive comparison with numerical simulation has been performed to validate model in both the long channel and short channel regimes.

Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

In this work, the high-k spacer is proposed to suppress the subthreshold characteristics variation of junctionless multigate transistor (JMT) with non-ideal sidewall angle for the first time. It is demonstrated that the variation of subthreshold characteristics induced by the changing sidewall angle is efficiently suppressed by high-k spacers due to the enhanced corner effect through the fringe capacitance, and the electrostatic integrity of JMTs is also improved at sub-22 nm gate length. Two key parameters of high-k spacer, the thickness and length, have been optimized in terms of the suppression of subthreshold characteristics variation. Then their optimal values are proposed. The benefit of high-k spacer makes JMTs more scalable.

Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors

In this work, the subthreshold characteristics of a junctionless multigate transistor (JMT) with a trapezoidal fin cross section are studied by three-dimensional simulations. The effects of sidewall angle (Θ) on subthreshold swing (SS) and drain-induced barrier lowering (DIBL) are evaluated and compared with the effects of doping concentration. The results show that SS and DIBL are strongly dependent on Θ and more seriously affected by Θ variation. Meanwhile, as compared with those observed in inversion-mode multigate MOSFETs (IM-MuGFETs), the variations in SS and DIBL in JMTs with sidewall angle are better suppressed. A design guideline is finally proposed to define the optimal parameters of JMTs for a given technology.

Double-gate tunneling FET with asymmetric gate structure and pocket source

In this paper, asymmetric gate structure and pocket source are proposed into the double-gate tunneling FET (DG TFET). Steeper average subthreshold swing (SS) and larger on currents are observed in the proposed TFET as compared with conventional TFET. The improvements are attributed to a larger volume tunneling due to the enhanced body electric field. In addition, threshold voltage adjustment is achieved by adjusting the pocket source thickness, which indicates the potential for supply voltage scaling.