Han Wui Then

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (ID) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase ID by more than 20X.

Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (LSIDE) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, TQW=10nm) body planar InGaAs device due to (i) narrow fin width (WFIN) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III–V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III–V FETs for future low power logic applications.

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5×1012 cm−2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE < 40 Å, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.

MOVPE III–V material growth on silicon substrates and its comparison to MBE for future high performance and low power logic applications

This research work demonstrates, for the first time, that the material quality of MOVPE III–V QWFET structures on Si can be matched to that of the best MBE III–V QWFET structures on Si. The MOVPE grown In<inf>0.53</inf>Ga<inf>0.47</inf>As QW layer on Si exhibits high Hall mobility of ∼8000cm²/V-s at 300K, matching that obtained by MBE growth on lattice matched InP (the “gold standard”).

Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (V CC ) ranging from 0.5v to 1.0v

In this paper for the first time, the logic performance of Schottky-gate In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFETs is measured and evaluated against that of advanced Strained Si MOSFETs from Vcc = 0.5 to 1.0V. The QWFET is shown to have measured drive current gain over the Si MOSFET for the entire Vcc range. Effective velocity (V<inf>eff</inf>) of the QWFET exhibits 4.6X–3.3X gain over the Si MOSFET. The high V<inf>eff</inf> enables 65% intrinsic drive current gain at V<inf>CC</inf> = 0.5V and 20% gain at V<inf>CC</inf> = 1.0V for the In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFET over that of Strained Si, despite 2.5x lower charge density.

Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al 0.83 In 0.17 N/AlN/GaN MOS-HEMT on SiC substrate

GaN is a promising material for LED lighting [1], high voltage power electronics [2] and high power RF applications [3]. GaN HEMT and MOS-HEMT with AlGaN [4] or AlInN [5] polarization layer have been widely studied. In this work we investigate the effects of Al_0.83In_0.17N polarization layer thickness scaling on the device characteristics of Al_0.83In_0.17N/AlN/GaN MOS-HEMTs on SiC substrates. We have experimentally observed “negative” capacitance and subthreshold swing (SS) steeper than 40 mV/dec in GaN MOS-HEMTs with thin Al_0.83In_0.17N polarization layer, where composition modulation of Al% and In% is observed.

High-performance low-leakage enhancement-mode high-K dielectric GaN MOSHEMTs for energy-efficient, compact voltage regulators and RF power amplifiers for low-power mobile SoCs

We have fabricated L_G=90nm high-K dielectric enhancement-mode (e-mode) GaN MOS-HEMT which shows low I_OFF=70nA/μm (V_D=3.5V, V_G=0V), low R_ON=490Ω-μm, high I_D,max=1.4mA/μm, and excellent power-added efficiency (PAE) of 80% at RF output power density (RF Pout) of 0.55W/mm (V_D=3.5V, f=2.0GHz). These results represent (i) >3.6X lower RON at equivalent breakdown voltage (BV_D) than industry-standard Si voltage regulator (VR) transistors, and (ii) >10% better PAE at matched RF Pout or >50% higher RF Pout at matched PAE than industry-standard GaAs RF power amplifier (PA) transistors, all at mobile SoC-compatible voltages. These results make GaN MOS-HEMTs attractive for realizing energy-efficient, compact voltage regulators and RF power amplifiers for mobile SoC. This work shows, for the first time, that the application space of GaN electronics can be expanded beyond the existing high-voltage power and RF electronics (e.g. automobile, power conversion, base-station, radar) to include low-power mobile SoCs.