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Featured researches published by Seung Hoon Sung.


international electron devices meeting | 2013

Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al 0.83 In 0.17 N/AlN/GaN MOS-HEMT on SiC substrate

Han Wui Then; Sansaptak Dasgupta; Marko Radosavljevic; L.A. Chow; Benjamin Chu-Kung; Gilbert Dewey; Sanaz K. Gardner; X. Gao; J. Kavalieros; Niloy Mukherjee; Matthew Hillsboro Metz; M. Oliver; Ravi Pillarisetty; Valluri Rao; Seung Hoon Sung; G. Yang; Robert S. Chau

GaN is a promising material for LED lighting [1], high voltage power electronics [2] and high power RF applications [3]. GaN HEMT and MOS-HEMT with AlGaN [4] or AlInN [5] polarization layer have been widely studied. In this work we investigate the effects of Al<sub>0.83</sub>In<sub>0.17</sub>N polarization layer thickness scaling on the device characteristics of Al<sub>0.83</sub>In<sub>0.17</sub>N/AlN/GaN MOS-HEMTs on SiC substrates. We have experimentally observed “negative” capacitance and subthreshold swing (SS) steeper than 40 mV/dec in GaN MOS-HEMTs with thin Al<sub>0.83</sub>In<sub>0.17</sub>N polarization layer, where composition modulation of Al% and In% is observed.


international interconnect technology conference | 2016

Resistance and electromigration performance of 6 nm wires

Jasmeet S. Chawla; Seung Hoon Sung; Stephanie A. Bojarski; Colin T. Carver; Manish Chandhok; Ramanan V. Chebiam; James S. Clarke; M. Harmes; Christopher J. Jezewski; M. J. Kobrinski; Brian Krist; Mona Mayeh; R. Turkot; Hui Jae Yoo

A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements showing line electrical resistance and electromigration as functions of material, conducting area, and interfaces are presented.


symposium on vlsi technology | 2015

High-performance low-leakage enhancement-mode high-K dielectric GaN MOSHEMTs for energy-efficient, compact voltage regulators and RF power amplifiers for low-power mobile SoCs

Han Wui Then; L.A. Chow; Sansaptak Dasgupta; Sanaz K. Gardner; Marko Radosavljevic; Valluri Rao; Seung Hoon Sung; G. Yang; Robert S. Chau

We have fabricated L<sub>G</sub>=90nm high-K dielectric enhancement-mode (e-mode) GaN MOS-HEMT which shows low I<sub>OFF</sub>=70nA/μm (V<sub>D</sub>=3.5V, V<sub>G</sub>=0V), low R<sub>ON</sub>=490Ω-μm, high I<sub>D,max</sub>=1.4mA/μm, and excellent power-added efficiency (PAE) of 80% at RF output power density (RF Pout) of 0.55W/mm (V<sub>D</sub>=3.5V, f=2.0GHz). These results represent (i) >3.6X lower RON at equivalent breakdown voltage (BV<sub>D</sub>) than industry-standard Si voltage regulator (VR) transistors, and (ii) >10% better PAE at matched RF Pout or >50% higher RF Pout at matched PAE than industry-standard GaAs RF power amplifier (PA) transistors, all at mobile SoC-compatible voltages. These results make GaN MOS-HEMTs attractive for realizing energy-efficient, compact voltage regulators and RF power amplifiers for mobile SoC. This work shows, for the first time, that the application space of GaN electronics can be expanded beyond the existing high-voltage power and RF electronics (e.g. automobile, power conversion, base-station, radar) to include low-power mobile SoCs.


international interconnect technology conference | 2015

Simple test vehicle for metal fill and resistance of sub-8nm nanowire

Seung Hoon Sung; Jasmeet S. Chawla; Colin T. Carver; Ramanan V. Chebiam; James S. Clarke; Chris Jezewski; Tristan A. Tronic; Bob Turkot; Hui Jae Yoo

Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabricated with existing silicon patterning recipes to achieve an electrical test vehicle that can test a range of metal candidates for interconnects. The vehicle is characterized using electron microscopy and electrical measurements.


international interconnect technology conference | 2015

Nickel silicide for interconnects

Kevin L. Lin; Stephanie A. Bojarski; Colin T. Carver; Manish Chandhok; Jasmeet S. Chawla; James S. Clarke; M. Harmes; Brian Krist; Hazel Lang; Mona Mayeh; Sudipto Naskar; John J. Plombon; Seung Hoon Sung; Hui Jae Yoo

Nickel silicide is an attractive option for interconnects at small dimensions because of its short electron mean free path and good electromigration behavior. Nickel silicide interconnects can be integrated using either a subtractive or damascene process. Precise control of final metal composition ratio is important for obtaining low resistivity, as shown in thin-film and patterned structure measurements.


Archive | 2011

Variable gate width for gate all-around transistors

Van H. Le; Ravi Pillarisetty; Jack T. Kavalieros; Robert S. Chau; Seung Hoon Sung


Archive | 2014

Trench confined epitaxially grown device layer(s)

Ravi Pillarisetty; Seung Hoon Sung; Niti Goel; Jack T. Kavalieros; Sansaptak Dasgupta; Van H. Le; Marko Radosavljevic; Gilbert Dewey; Han Wui Then; Niloy Mukherjee; Matthew V. Metz; Robert S. Chau


Archive | 2014

Nonplanar iii-n transistors with compositionally graded semiconductor channels

Han Wui Then; Sansaptak Dasgupta; Marko Radosavljevic; Benjamin Chu-Kung; Seung Hoon Sung; Sanaz K. Gardner; Robert S. Chau


Archive | 2014

Group iii-n transistors on nanoscale template structures

Han Wui Then; Sansaptak Dasgupta; Marko Radosavljevic; Benjamin Chu-Kung; Sanaz K. Gardner; Seung Hoon Sung; Robert S. Chau


Archive | 2015

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

Sansaptak Dasgupta; Han Wui Then; Marko Radosavljevic; Niloy Mukherjee; Niti Goel; Sanaz K. Gardner; Seung Hoon Sung; Ravi Pillarisetty; Robert S. Chau

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