Han-Yu Chen

Small-Signal Modeling of SiGe HBTs Using Direct Parameter-Extraction Method

A simple and accurate parameter-extraction method of a high-frequency small-signal SiGe heterojunction bipolar transistor model is proposed in this paper. It was found that, without taking the intrinsic circuit elements into account, the conductance of the substrate network will be underestimated, while the susceptance of the substrate network will be overestimated. Therefore, a new extraction technique of the substrate-network parameters was developed, which has taken the intrinsic circuit elements into consideration. Transforming the intrinsic equivalent circuit into its common-collector configuration, all the intrinsic circuit elements are extracted directly from the measured S-parameters without any numerical optimization. Two formulas used to determine the intrinsic base resistance are presented, which is followed by an accuracy-improvement procedure to achieve a better accuracy of the extraction results. Simplified formulas to determine the base-emitter resistance, base-emitter capacitance, transconductance, and excess phase delay are also presented. The proposed method is validated with SiGe HBTs fabricated with a 0.35-mum BiCMOS technology from 1 to 30 GHz. The agreements between the measured and modeled data are excellent in the desired frequency range over a wide range of bias points

Linearity and power characteristics of SiGe HBTs at high temperatures for RF applications

In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures.

An improved parameter extraction method of SiGe HBTs' substrate network

In this letter, an improved method for substrate network parameter extraction of SiGe heterojunction bipolar transistors (HBTs) is proposed. It is found that, without taking the intrinsic circuit elements into consideration, the conductance of substrate network will be underestimated while the susceptance of substrate network will be overestimated. Therefore, an iteration procedure is developed to determine the intrinsic circuit elements of SiGe HBTs first. The intrinsic circuit elements are then applied to remove their influence on the substrate network parameter extraction. Compared with the conventional method, the proposed one can avoid some unphysical modeling results and provide reliable substrate network parameters.

A Novel Approach for Parameter Determination of HBT Small-Signal Equivalent Circuit

Direct parameter extraction is believed to be the most accurate method for equivalent-circuits modeling of heterojunction bipolar transistors (HBTs). Using this method, the parasitic elements, followed by the intrinsic elements, are determined analytically. Therefore, the quality of the extrinsic elements extraction plays an important role in the accuracy and robustness of the entire extraction algorithm. This study proposes a novel extraction method for the extrinsic elements, which have been proven to be strongly correlated with the intrinsic elements. By utilizing the specific correlation, the equivalent circuit modeling is reduced to an optimization problem of determining six specific extrinsic elements. Converting the intrinsic equivalent circuit into its common-collector configuration, all intrinsic circuit elements are extracted using exact closed-form equations for both the hybrid-π and the T-topology equivalent circuits. Additionally, a general explicit equation on the total extrinsic elements is derived, subsequently reducing the number of optimization variables. The modeling results are presented, showing that the proposed method can yield a good fit between the measured and calculated S parameters.

Layout design of high-quality SOI varactor

This paper presents the geometry effect on the characteristics of accumulation type SOI varactor with mesa-isolation technology. Constant gate area varactors with various geometry condition were implemented to investigate the effects of layout design parameters on overall varactor performance. Physical and mathematic analysis based on the measurement results show that parasitic capacitance at the edge of active region seriously degrades the device quality factor at smallest gate length. The optimized SOI varactor has a quality factor Q of about 150/GHz/pF at medium gate length varactor. The experiment result can serve as a design reference for high-quality SOI varactors.

Impact of body bias on the high frequency performance of partially depleted SOI MOSFETs

SOI MOS technology has been slated as the future ULSI technology because of its advantages in terms of speed, isolation, density, yield and performance. The superior speed advantage of the SOI devices has attracted much attention in both digital and radio frequency applications. In recent years, a number of direct current analysis based on the body-tied configurations of SOI devices have been reported. It has been confirmed that the body-tied configuration is one of the most effective and practical methods of suppressing the floating body effect and realizing the stable operation in SOI circuits, because the body potential of an SOI MOSFETs is fixed. Body-tied configuration SOI MOSFET has therefore been employed for some crucial parts in circuits that require high stability such as dynamic circuits. However, to this date, high frequency performance of body-tied configuration SOI devices is mainly focused on the dynamic-threshold MOSFET in which the body of the device is tied to the gate. This particular device configuration makes the analysis of small-signal model complicated and does not reveal much insight into the body bias effect on the device high frequency performance. In this study, we investigated the impacts of body bias on the high frequency performance of PD SOI MOSFET and showed, for that both fT and fmax are dependent on the body bias.

Extraction of Correlated Base and Collector Current RF Noise Sources in SiGe HBTs

A method for extracting current noise sources in SiGe HBTs is proposed in this work. The base current noise, collector current noise and their correlation are extracted after removing the noise contribution from the extrinsic elements of devices. We simplify the extraction procedure by simple calculations of the four-port Y-parameters of the extrinsic circuit. The proposed procedure prevents the complicated calculation through repeated two-port noise circuit analysis. The four-port Y-parameters are calculated through the use of corresponding operands following their definition. The proposed four-port Y-parameters calculation method is much easy to implement in the mathematic program.

RF noise modeling of SiGe HBTs using four-port de-embedding method

A complete extraction technique of SiGe HBTs is developed to extract the base and collector current noises and their correlation. Unlike conventional methods, a four-port noise de- embedding technique is used to remove the influence of extrinsic elements. From the extraction results, we found that the base current noise and collector current noise can not be modeled well using 2qIB and 2qlc, respectively. By modifying the expressions of current noises, the noise performance of a SiGe HBT can be modeled more accurately.

P-channel SONOS Transient Current Modeling for Program and Erase

Transient current models with time and field dependence are proposed. The time dependence follows asymptotic t-1 behavior with slower tunneling rate for erase (ERS) than program (PGM). The field dependence follows FN tunneling in higher field for PGM and intermediate field for ERS with relatively higher corner field for saturation. The models have been justified for P-channel SONOS (P-SONOS) with splits of ONO scheme.

An analysis of base current effect on the anomalous dip of scattering parameter S/sub 12/ in SiGe HBTs

In this paper, the anomalous dip in scattering parameters S/sub 12/ of SiGe HBTs is explained quantitatively for the first time. It was found that under constant collector-emitter voltage (V/sub CE/), an increase of base current (which corresponds to an increase of base-emitter capacitance (C/spl pi/) enhances the anomalous dip.