Wen-Shiang Liao

Investigation of Reliability Characteristics in NMOS and PMOS FinFETs

Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = Hfin/Wfin = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (Vcc) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at Vcc = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.

PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD-

In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been successfully fabricated. The performance improvements of devices with a gate length (Lg )of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least 50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows 32% current gain for Lg = 40 nm PMOS with the thinnest 9 A Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance.

\hbox{SiN}_{x}

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Stressing Layer

A high-aspect-ratio 3D multi-gate n-channel fin-shaped field effect transistor (FinFET) has been integrated with a stressor of a highly tensile nitride film as the initial inter layer dielectric capping layer upon a (110)-orientated silicon-on-insulator wafer. Drastically enhanced electrical performances, such as 190% enhancement of peak channel mobility, 91% of peak transconductance, and 34% of saturation current, etc., are achieved for an NMOS FinFET with a gate length of 90 nm. The Ioff-Ion universal curve also demonstrates an extraordinary drive current gain of 26%. Moreover, the hot carrier injection lifetime can be increased from 7.78 × 102 to 5.26 × 103 year (yr) due to the incorporation of this high-tensile contact etching stop layer and relaxation of the Si crystalline channel layer.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

The effects of mechanical stress on the dc and high-frequency performances of laterally diffused MOS (LDMOS) transistors with different layout structures were investigated by using the wafer bending method. A 3.1% peak cutoff frequency (fT) enhancement is achieved for the multifinger device under 0.051% biaxial tensile strain. For LDMOS with annular layout, the fT enhancement is increased to 3.7% due to the various channel directions. Our results suggest the strain technology can be adopted in LDMOS for RF applications. The transconductance and gate capacitance were also extracted to clearly demonstrate the fT variations.

Drive current and hot carrier reliability improvements of high-aspect-ratio n-channel fin-shaped field effect transistor with high-tensile contact etching stop layer

Silicon capping layer is a useful dielectric smoothing the interface integrity between gate dielectric and SiGe deposition layer in nano-scale process technology and reducing the possibility of Ge atom diffusion into the gate dielectric. However, the junction performance in reverse saturation current is suffered. Through the deliberate pattern design, the fringe junction leakage for MOSFET device was effectively extracted. The thicker Si capping layer well prevents Ge atom from diffusing into gate dielectric, but causes more fringe junction leakage at source/drain sites.

LDMOS Transistor High-Frequency Performance Enhancements by Strain

In this study, the process technology of contact-etching stop-layer (CESL) with LPCVD or PECVD is performed by interlayer-dielectric-SiNx stressing layer to form the tensile or compressive strained n/p MOSFETs. Because the strain effect on MOSFET devices is finite, the promoting performance of source/drain current is increased more while the channel lengths of the devices are decreased more. This phenomenon is obviously observed with devices, width/length=W/L= 10/10 and 10/.08 (µm/µm). Moreover, the trend evidence for tensile strain benefited to nMOSFETs and pMOSFETs, but for compressive strain favoring pMOSFTEs and not hugely degrading nMOSFETs, is also achieved.

Nano-scale Si-capping thicknesses impacting junction performance on silicon substrate

This paper proposes a cost-effective RF power cell manufactured in an advanced 0.13 um CMOS technology. Without adding additional masks, cost, and process, the power performance can be improved just by using the standard N-well and shallow-trench-isolation processes to form a higher resistive region. This ldquoPseudo-Drainrdquo structure increases the breakdown voltage to more than 4.3V and is higher than the value of 2.5V of the standard 0.13 um core-MOS transistor. This transistor exhibits a high fTtimesBVDS product of 352 for CMOS power FETs. Cutoff frequency and maximum oscillation frequency of 83 GHz and 124 GHz were achieved at a drain bias of 1.2V, respectively; while the maximum power gain, output power and power-added efficiency were 25.6 dB, 19 dBm, and 55%, respectively. Good RF linearity and noise figure were also obtained, as demonstrated by an OIP3 and NFmin of 28.32 dBm and 0.4 dB. The presented RF power transistor is cost effective and can be used for power amplifier integration in RF-CMOS SOC.

CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication

It is demonstrated that the appropriate external mechanical stress applied by the conventional IC chips package straining can enhance device and circuit performance. A drain current enhancement of 4.9% at saturation is observed for 90-nm-node n-channel metal oxide semiconductor field effect transistor (nMOSFET) under a biaxial tensile strain of 0.096%. The current enhancement is nearly independent of gate width for 90-nm-node logic devices. Moreover, there is a 2.3% speed enhancement for a 90 nm-node logic ring oscillator using a parallel layout under the same biaxial tensile strain of 0.096%.

Novel Pseudo-Drain (PD) RF power cell in 0.13 um CMOS technology

This work demonstrates the isolation integrity between gate contact and source or drain contact with the variety of source/drain extension lengths. The trend of isolation capability not only linearly followed the extension length, but related to the formation of liner spacer. As the channel width (W<inf>fin</inf>=0.11μm) was fixed, the I<inf>GD</inf> leakage at channel lengths L<inf>g</inf>= 0.24, 0.16, and 10μm with L<inf>SDE</inf>= 160nm is larger as V<inf>G</inf>= −Vcc. However, the I<inf>GD</inf> value with L<inf>SDE</inf>= 60nm is larger, located at L<inf>g</inf>= 0.24, 0.12, and 0.5μm as the same voltage bias.