Pei-Ying Du

Radically extending the cycling endurance of Flash memory (to > 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage

Flash memory endurance is limited by the tunnel oxide degradation after repeated P/E stressing in strong electric field. Thermal annealing should be able to repair the oxide damage but such theory cannot be tested in real time since completed device cannot endure high temperature > 400°C and long baking time is impractical for real time operation. In this work, we propose and demonstrate a novel self-healing Flash, where a locally high temperature (>800°C), short time (ms) annealing is generated by a built-in heater. By modifying the word line (WL) from a single-ended to a double-ended structure, the WL can carry a current to generate Joule heating; and the proximity of the gate can readily heat the tunnel oxide of the Flash device, annealing out the damage caused by P/E cycling. We discover that a BE-SONOS charge-trapping NAND Flash device can be quickly annealed within a few milliseconds. With this novel technique, we demonstrate a record-high endurance of >100M (108) P/E cycles with excellent post-100M-cycle retention. Interestingly, the WL heater can be used to achieve faster erasing although normally FN tunneling should be temperature-independent. At the extreme temperature achieved in our heating-while-erasing experiments electron de-trapping from the charge trapping nitride, accompanying hole FN tunneling, also occurs, resulting in faster erasing. Finally, a novel design architecture for implementing the self-healing Flash memory is proposed.

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method—Part I: Fundamental Theory and Applications to Study of the Trapped Charge Vertical Location and Capture Efficiency of SONOS-Type Devices

Using a recently developed gate-sensing and channel- sensing (GSCS) transient analysis method, we have studied the detailed charge-trapping behavior for SONOS-type devices. By adding gate sensing to the conventional channel sensing, the two variables (total charge Qtot and mean vertical location x circ) can be solved simultaneously. By using this powerful new tool on several SONOS-type structures, we have studied the charge centroid as well as the capture efficiency of various SONOS devices. Our results clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For the first time, we show that nitride 7 nm or thicker can essentially capture electrons with 100% efficiency up to a density of Qtot ~1013 cm-2. Structures without top blocking oxide suffer from hole back tunneling and show apparent low electron capture efficiency, which led to confusion in the past. Moreover, multilayer stacks of nitride-trapping layers do not provide more efficient interfacial traps.

Understanding barrier engineered charge-trapping NAND flash devices with and without high-K dielectric

Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution (Vt-time) of any BE-CTNF device during programming/erasing can be accurately simulated. The model is validated by experimental results from bandgap-engineered SONOS (BE-SONOS) and various structures using Al2O3 top-capping layer. Using this model, various structures of BE-CTNF with high-K tunneling or blocking dielectric are investigated. Furthermore, the low-field tunneling current for various structures are simulated, providing theoretical foundations for retention and read disturb optimization.

A Novel Gate-Sensing and Channel-Sensing Transient Analysis Method for Real-Time Monitoring of Charge Vertical Location in Sonos-Type Devices and its Applications in Reliability Studies

By using poly-gate-sensing in addition to the conventional channel-sensing for Vt (or VFB) presents a novel transient analysis method that is very powerful to monitor the trapped charge vertical location in real time. The sensing in both modes provides two equations that are suitable to solve for two variables - the charge density (Q) and the average charge vertical location (x). Without the second equation (from poly-gate-sensing) Q and x cannot be de-convoluted. The power of this new technique is demonstrated by several examples of reliability studies for SONOS-type devices. The charge trapping efficiency of silicon nitride of different thickness is examined. The charge migration during program/erase cycling and data retention information is observed for the first time using this new tool. The method presented in this work is indeed a powerful tool for detailed understanding of trapping dynamics.

A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-Type Devices

For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -VG stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.

Reliability and Processing Effects of Bandgap-Engineered SONOS (BE-SONOS) Flash Memory and Study of the Gate-Stack Scaling Capability

In this paper, the reliability properties of bandgap-engineered SONOS (BE-SONOS) devices with various processing methods are extensively studied. BE-SONOS employs a multilayer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as a bandgap-engineered tunneling barrier that provides an efficient hole-tunneling erase but eliminates the direct-tunneling leakage. BE-SONOS can overcome the fundamental limitation of the conventional SONOS, for which fast erase speed and good data retention cannot be simultaneously achieved. In this paper, a comprehensive understanding of BE-SONOS reliability is reported, including the processing effects of the critical ONO barrier (O1/N1/O2), the trapping layer (N2), and the top blocking oxide (O3). Moreover, the capability of dielectric scaling is also evaluated. Lower P/E voltages, good P/E cycling endurance, and data retention are maintained when N2 and O3 are further scaled to 60 . The results in this paper provide design and processing guidelines for optimizing the performance and reliability of BE-SONOS flash memory devices.

A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space

This work proposes a novel dual-channel 3D NAND Flash that exhibits both n-channel and p-channel NAND characteristics. The NAND is junction-free without dopant inside the array. Unlike the conventional 3D NAND, the drain side near SSL is N+ doped junction, while source side near GSL is P+ junction. A positive pass-gate read voltage (Vpass, r) induces n-type virtual source/drain for the center WLs, giving an n-channel behavior. On the other hand, a negative Vpass, r induces p-type virtual source/drain, giving the p-channel behavior. Both n- and p-channel reads produce excellent Id-Vg characteristics with very small leakage current. The advantage of this device is that the carrier source of both +FN programming and -FN erasing can be readily provided by either N+ drain or P+ source, respectively, without waiting for the GIDL generated minority carrier for the floating-body 3D NAND. This gives a much faster +/- FN speed than conventional 3D NAND. Moreover, both +FN and -FN can find suitable inhibit method, enabling a novel bit-alterable Flash memory. We have successfully compared, for the first time, two sensing methods (n- and p-channel read) and identified the trapped charge in the space between WLs. This not only provides characterization of charge lateral profile but also a new opportunity to create another storage node (in WL space) inside the array.

Study of the Gate-Sensing and Channel-Sensing Transient Analysis Method for Monitoring the Charge Vertical Location of SONOS-Type Devices

The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q ) and the average charge vertical location (x ). In this paper, the principle of this method is discussed in detail. Several factors that affect the measurement accuracy are also analyzed. The power of this method is demonstrated by program/erase cycling and data retention tests. This method is indeed a powerful tool for detailed understanding of trapping dynamics.

Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices

Barrier-engineered charge-trapping NAND Flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multilayer barrier is derived using the Wentzel-Kramers-Brillouin approximation. The rigorously derived analytical form is valid for both electron and hole tunnelings, as well as for any barrier composition. With this, the time evolution (Vt-time) of any BE-CTNF device during programming/erasing can be accurately simulated. The model is validated by experimental results from bandgap-engineered silicon-oxide-nitride-oxide-silicon and various structures using an Al2O3 top-capping layer. Using this model, various structures of BE-CTNF with high-κ tunneling or blocking dielectric are investigated. Finally, the impacts of barrier engineering on incremental-step pulse programming are examined.

A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface

For Solid-State Drive (SSD) applications cycling endurance of NAND flash is a critical challenge. In this work the endurance reliability of BE-SONOS NAND is thoroughly examined. Using dual CV/IV tests the impact of interface state (Dit) generation/annealing and real charge trapping (Q) on the endurance degradation has been clearly identified. For BE-SONOS with pure thermal oxide O1, the endurance degradation mainly comes from Dit generation at Si/O1 interface, while charge trapping in the thin ONO barrier is negligible even after 100K cycles of stressing. Meanwhile, the high-temperature VT loss mainly comes from interface state annealing, while the real charge loss due to electron de-trapping is much smaller. This indicates that our nitride-trapping device has “deep” traps that well retain charges even after the tunnel barrier is damaged. Based on this understanding, we have introduced nitrided O1 to strengthen the Si/O1 interface, and both the endurance and retention are greatly improved. We demonstrate high-endurance BE-SONOS NAND devices of P/E ≫ 5K for MLC and P/E ≫ 100K for SLC operations with excellent retention, promising for solid-state drive (SSD) applications.