Bassel Hanafi

A Q-Band Amplifier Implemented with Stacked 45-nm CMOS FETs

A stacked FET, single-stage 45-GHz (Q-band) CMOS power amplifier (PA) is presented. The design stacked three FETs to avoid breakdown while allowing a high supply voltage. The IC was implemented in a 45-nm CMOS SOI process. The saturated output power exceeds 18 dBm from a 4-V supply. Integrated shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The amplifier occupies an area of 450x500 im² including pads, while achieving a maximum power-added-efficiency (PAE) above 20%.

Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS

A 45 GHz active phase-shift Doherty PA is proposed and implemented in 45-nm SOI CMOS. The quarter wave-length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5%, while reducing the die area. Use of slow-wave coplanar waveguides (S-CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two-stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase-shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm2, and at 6-dB back-off power, the PAE is 21%.

A 34% PAE, 18.6dBm 42–45GHz stacked power amplifier in 45nm SOI CMOS

A two-stack 42-45GHz power amplifier is implemented in 45nm SOI CMOS. Transistor stacking allows increased drain biasing to increase output power. Additionally, shunt inter-stage matching is used and improves PAE by more than 6%. This amplifier exhibits 18.6dBm saturated output power, with peak power gain of 9.5dB. It occupies 0.3mm2 including pads while achieving a peak PAE of 34%. The PAE remains above 30% from 42 to 45GHz.

A 45GHz Doherty power amplifier with 23% PAE and 18dBm output power, in 45nm SOI CMOS

A 45GHz Doherty power amplifier is implemented in 45nm SOI CMOS. Two-stack FET amplifiers are used as main and auxiliary amplifiers, allowing a supply voltage of 2.5V and high output power. The use of slow-wave coplanar waveguides (CPW) improves the PAE and gain by approximately 3% and 1dB, and reduces the die area by 20%. This amplifier exhibits more than 18dBm saturated output power, with peak power gain of 7dB. It occupies 0.64mm2 while achieving a peak PAE of 23%; at 6dB back-off the PAE is 17%.

Spatially power-combined W-band power amplifier using stacked CMOS

A spatially power-combined CMOS SOI power amplifier at 94 GHz is reported. The CMOS chip contains a 2×4 array of pseudo-differential power amplifiers, and is integrated with a microstrip antenna array on a quartz superstrate. A 13-stage amplifier chain is implemented to provide gain, using stacked NFETs in a 45-nm CMOS SOI process. The amplifier array outputs a power of 24 dBm (250 mW) and the chip-quartz assembly radiates an equivalent isotropic radiated power (EIRP) of 33 dBm at 94 GHz. This is the highest radiated power reported from a Silicon CMOS active array transmitter at W-band, and the highest W-band output power from a single CMOS chip.

Transmission of Signals With Complex Constellations Using Millimeter-Wave Spatially Power-Combined CMOS Power Amplifiers and Digital Predistortion

This paper reports the generation, amplification, and radiation of modulated signals at 45 GHz using a single-chip CMOS power amplifier coupled to a 2 × 2 antenna array. Using digital predistortion, complex constellations were demonstrated for wide modulation bandwidth, which allows high data rates to be transmitted in a spectrally efficient manner. After predistortion, a 98-MS/s 1024-QAM signal with peak-to-average power ratio of 7 dB was demodulated with an error vector magnitude of 1.3%. The measured equivalent isotropically radiated power was 26.2 dBm. The corresponding average RF power produced by the CMOS chip, considering a simulated antenna gain of 12 dB, was 14.2 dBm.

A CMOS 45 GHz power amplifier with output power > 600 mW using spatial power combining

A single-chip 45 GHz power amplifier implemented in 45nm CMOS SOI is described, which feeds its RF output power to a 2×2 antenna array on an accompanying printed circuit board. The chip results in a maximum RF output power of 28 dBm (630 mW), and the system achieves a peak equivalent isotropic radiated power (EIRP) of 10 Watts (for a 2×2 antenna gain of 12 dB). The power amplifier is composed of 4 unit amplifier cells, each of which has pseudo-differential outputs. Stacking of 4 transistors was used in order to increase allowable voltage swings. The overall chip dimensions are 4.5 × 2.5 mm2. The DC power consumption was 4.9 W from 5.5 V and 4.0 V supplies, corresponding to a power-added efficiency of 13.5%.

A W-band stacked FET power amplifier with 17 dBm P sat in 45-nm SOI MOS

A 90GHz power amplifier implemented with three series-connected (stacked) FETs in 45-nm SOI CMOS is reported. Stacking FETs allows increasing voltage handling capability of circuits with highly scaled CMOS transistors. This work shows for the first time that the stacking strategy is effective up to W band. The amplifier achieves power gain of 8 dB at 91 GHz with 3 dB bandwidth of 18 GHz using a supply voltage of 4.2 V. It delivers saturated output power of 17.3 dBm in 88-90 GHz range with peak PAE of 9 %. The PA chip occupies 0.256 mm2 including the pads. This chip demonstrates the highest output power from a CMOS PA in this frequency regime.

A 45-GHz Si/SiGe 256-QAM transmitter with digital predistortion

The operation of a 45-GHz, Silicon/Silicon Germanium transmitter chipset including a 2×2 power amplifier (PA) array and an I/Q modulator with digital predistortion (DPD) linearization is demonstrated. The 2×2 PA array is implemented in a 45-nm SOI CMOS process and feeds a 2×2 antenna array implemented on a printed circuit board (PCB). The I/Q modulator is implemented in a 120-nm SiGe BiCMOS process where the LO input and RF output are also wire-bonded to a PCB and is programmed through an FPGA to compensate I/Q imbalance and LO leakage. The Si/SiGe transmitter chipset achieves 2.67% EVM at 9.375-MS/s symbol rate with 256-QAM, and 3.68% EVM at 25-MS/s symbol rate with 64-QAM. It produces an average EIRP of 28.6 dBm and consumes 1.7 W from the PA and 322 mW from the I/Q modulator after DPD.

-Band Spatially Combined Power Amplifier Arrays in 45-nm CMOS SOI

This paper reports 45-GHz power amplifier (PA) arrays implemented in 45-nm CMOS silicon-on-insulator, coupled to antenna arrays to enable free-space power combining. A single CMOS chip (2.5 × 4.5 mm2) containing eight-unit PAs was developed and its output was fed to a 2 × 2 array of differentially fed patch antennas on a printed circuit board. This array provided an equivalent isotropic radiated power (EIRP) of 40 dBm at 45 GHz with 28 dBm of total RF power generated by the chip. A larger array, composed of four CMOS chips and feeding a 2 × 8 array of antennas, was shown to deliver an EIRP of 50 dBm at 45 GHz, while generating a total RF power of 33 dBm together with an antenna array gain of 17 dB. The dc power consumptions for the 2 × 2 and the 2 × 8 arrays were 4.9 and 18 W, respectively, with estimated peak power-added efficiencies of 13.5% and 10.7%.