Amir Agah

Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS

A 45 GHz active phase-shift Doherty PA is proposed and implemented in 45-nm SOI CMOS. The quarter wave-length transmission line at the input of the auxiliary amplifier is replaced by an amplifier, increasing the gain and PAE by more than 1 dB and 5%, while reducing the die area. Use of slow-wave coplanar waveguides (S-CPW) improves the PAE and gain by approximately 3% and 1 dB, and further reduces the die area. Two-stack FET amplifiers are used as the main and auxiliary amplifiers, allowing a supply voltage of 2.5 V and increasing the output power. The active phase-shift Doherty amplifier demonstrates a peak power gain and PAE of 8 dB and 20% at 45 GHz. It occupies 0.45 mm2, and at 6-dB back-off power, the PAE is 21%.

Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS

Gate resistance significantly limits the output power and power-added efficiency of stacked-FET power amplifiers in 45 nm SOI CMOS above 60 GHz. A multi-drive stacked-FET approach is proposed to improve the output power and efficiency. An analysis of conventional and multi-drive stacked-FET PAs demonstrates the performance improvement. A multi-drive three-stack PA is implemented in 45 nm SOI CMOS for 90 GHz operation occupying 0.23 mm 2 . This PA achieves more than 19 dBm output power with peak PAE of 14% and 12 dB gain at 90 GHz using a 3.4 V power supply.

A 34% PAE, 18.6dBm 42–45GHz stacked power amplifier in 45nm SOI CMOS

A two-stack 42-45GHz power amplifier is implemented in 45nm SOI CMOS. Transistor stacking allows increased drain biasing to increase output power. Additionally, shunt inter-stage matching is used and improves PAE by more than 6%. This amplifier exhibits 18.6dBm saturated output power, with peak power gain of 9.5dB. It occupies 0.3mm2 including pads while achieving a peak PAE of 34%. The PAE remains above 30% from 42 to 45GHz.

A 45GHz Doherty power amplifier with 23% PAE and 18dBm output power, in 45nm SOI CMOS

A 45GHz Doherty power amplifier is implemented in 45nm SOI CMOS. Two-stack FET amplifiers are used as main and auxiliary amplifiers, allowing a supply voltage of 2.5V and high output power. The use of slow-wave coplanar waveguides (CPW) improves the PAE and gain by approximately 3% and 1dB, and reduces the die area by 20%. This amplifier exhibits more than 18dBm saturated output power, with peak power gain of 7dB. It occupies 0.64mm2 while achieving a peak PAE of 23%; at 6dB back-off the PAE is 17%.

Spatially power-combined W-band power amplifier using stacked CMOS

A spatially power-combined CMOS SOI power amplifier at 94 GHz is reported. The CMOS chip contains a 2×4 array of pseudo-differential power amplifiers, and is integrated with a microstrip antenna array on a quartz superstrate. A 13-stage amplifier chain is implemented to provide gain, using stacked NFETs in a 45-nm CMOS SOI process. The amplifier array outputs a power of 24 dBm (250 mW) and the chip-quartz assembly radiates an equivalent isotropic radiated power (EIRP) of 33 dBm at 94 GHz. This is the highest radiated power reported from a Silicon CMOS active array transmitter at W-band, and the highest W-band output power from a single CMOS chip.

A 11% PAE, 15.8-dBm two-stage 90-GHz stacked-FET power amplifier in 45-nm SOI CMOS

A two-stage 90-GHz stacked-FET power amplifier is implemented in 45-nm SOI CMOS. Dual supply operation supports high gain, power and efficiency in the two-stage design. The amplifier exhibits greater than 15.8 dBm saturated output power with 10 dB peak power gain and achieves a record peak PAE of 11%. The PAE remains above 8% from 86 to 94 GHz. It occupies 0.05 mm2 excluding pads.

A W-band stacked FET power amplifier with 17 dBm P sat in 45-nm SOI MOS

A 90GHz power amplifier implemented with three series-connected (stacked) FETs in 45-nm SOI CMOS is reported. Stacking FETs allows increasing voltage handling capability of circuits with highly scaled CMOS transistors. This work shows for the first time that the stacking strategy is effective up to W band. The amplifier achieves power gain of 8 dB at 91 GHz with 3 dB bandwidth of 18 GHz using a supply voltage of 4.2 V. It delivers saturated output power of 17.3 dBm in 88-90 GHz range with peak PAE of 9 %. The PA chip occupies 0.256 mm2 including the pads. This chip demonstrates the highest output power from a CMOS PA in this frequency regime.

A 42 to 47-GHz, 8-bit I/Q digital-to-RF converter with 21-dBm P sat and 16% PAE in 45-nm SOI CMOS

A novel stacked FET digital-to-RF converter is implemented in 45-nm SOI CMOS, which shares DC current through an I/Q digital-to-analog converter (DAC), I/Q mixer, and stacked-FET PA to provide high output power. The proposed architecture transmits at 1.25 Gbps for QPSK at 45GHz. This transmitter exhibits a 21.3-dBm saturated output power, while achieving a peak PAE of 16%. The circuit occupies 0.3 mm2 including pads, while the PAE and Psat remains above 13% and 18 dBm from 42 to 47 GHz.

High-speed, High-efficiency millimeter-wave transmitters at 45 GHz in CMOS

Millimeter-wave power amplifiers realized in CMOS processes have demonstrated output power and power added efficiency exceeding 20 dBm and 30%, respectively. We describe efforts to achieve high power and high efficiency for mm-wave transmitters and linearize mm-wave PAs in fineline CMOS processes. We will present novel circuit approaches based on Doherty amplifiers and digital pre-distortion of high-power mm-wave CMOS PA to demonstrate low error-vector magnitude (EVM).