Herman Oprins

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Improved Thermal Performance of AlGaN/GaN HEMTs by an Optimized Flip-Chip Design

AlGaN/GaN high electron mobility transistors (HEMT) on sapphire substrates have been studied for their potential application in RF power applications; however, the low thermal conductivity of the sapphire substrate is a major drawback. Aiming at RF system-in-a-package, the authors propose a flip-chip-integration approach, where the generated heat is dissipated to an AlN carrier substrate. Different flip-chip-bump designs are compared, using thermal simulations, electrical measurements, micro-Raman spectroscopy, and infrared thermography. The authors show that a novel bump design, where bumps are placed directly onto both source and drain ohmic contacts, improves the thermal performance of the HEMT

Temperature dependent electrical characteristics of through-si-via (TSV) interconnections

In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25–150°C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSV C-V characteristics are analyzed to extract the oxide charges. It is confirmed that the depletion behavior of TSV can be exploited to reduce TSV capacitance even at higher temperatures. In addition, lumped RC model of the TSV for circuit simulations is enhanced by incorporating measured TSV resistance and capacitance change due to temperature. The results are corroborated with the 2D/3D Ring Oscillator (RO) measurements at different temperatures.

Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. The complexity of the interconnection structures, combined with the reduced thermal spreading in the thinned dies and the poorly thermally conductive adhesives complicate the thermal behavior of a stacked die structure. The same dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die package compared to a single die package. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, a steady state and transient analysis is presented for hot spots in 3D stacked structures. For this analysis, dedicated test chips with integrated heaters and temperature sensors are used to assess the temperature profile in the different tiers of the stack and to investigate the impact of TSVs on the temperature profile. This experimental set-up is used to evaluated and improve the thermal models for the 3D stacks.

Practical chip-centric electro-thermal simulations

Full-chip dynamic electro-thermal simulation is achieved by coupling a circuit simulator and a thermal solver. By letting both simulations run with their specific time-step, a higher computational efficiency is achieved. A scheduler synchronizes temperatures in the circuit simulator and dissipation patterns in the thermal solver on an dasiaas-necessarypsila basis. The 3D geometry for the thermal solver is generated automatically from the layout data-base and cross-referenced to the netlist to allow automatic extraction of power-dissipation from circuit simulations. In order to obtain realistic thermal responses for smart-power chips containing large driver transistors, it is essential to define the boundary conditions appropriately and account for package and PCB transients. To do so, the simulation domain is extended to cover the full package body, and uniform boundary conditions are defined to account for the thermal impedance of the PCB and for convection and radiation. Validation results are shown for the case of an SOIC package. Work is on-going on QFN and other power-packages.

Compact thermal modeling of hot spots in advanced 3D-stacked ICs

This paper presents a new generic methodology used to determine a parameterized compact thermal model for 3-D stacked integrated circuits (3D-SIC). The method allows to calculate the thermal distribution due to hot spots in the die stack. This approach is applied to different case studies of stacked dies configurations. In order to demonstrate the method, a fully generic non-uniform heat sources “grid” with grid size of 100 μm has been considered. With this approach it is possible to derive an easy-to-use, fast prediction tool that, together with a user friendly graphical interface, allows to obtain the temperature distribution in the dies with good accuracy. Parameters such as the structure geometry, the thermal properties of the materials involved and the effects of the presence of a package resistance are investigated. It is demonstrated that this tool can be used for a fast optimization for the structural parameters, thus helping to design a 3-D die stack when a need for thermal management arises.

Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

3D-TSV technologies promise increased system integration at lower cost and reduced footprint. One of the most likely applications of 3D technology is the integration DRAM-on-logic. Thermal management issues are considered one of the potentially showstoppers for 3D-integration. In this paper, we present a thermal experimental and modeling characterization of a packaged DRAM on logic stack. The DRAM die is stacked to the thinned logic die (25μm) using CuSn microbumps. For the experimental characterization a dedicated logic chip with integrated heaters and sensors is used. The thermal impact of logic hot spot dissipation on the temperature profile of the DRAM and the logic die is experimentally characterized in a dedicated socket using two experimental configurations mimicking a high power and a low power configuration respectively. The use of those 2 different experimental configurations of the packaged stack allows the calibration of a detailed finite element thermal model. The calibrated thermal models are used to evaluate the impact of the effective thermal conductivity of the microbump and underfill layer and the impact of the logic die thickness on the temperature distribution in the logic and DRAM die for different cooling configurations of the die stack.

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.

Convection heat transfer in electrostatic actuated liquid droplets for electronics cooling

In this paper, the internal flow and heat transfer inside the electrostatic actuated droplets are studied for different droplet velocities by means of detailed flow computations. It is shown that the internal droplet flow exhibits a parabolic characteristic at one hand and that the presence of two convection cells decreases the heat transfer to the lower part of the droplet, thereby limiting the overall heat transfer through the droplet. A typical enhancement of the heat transfer with a factor 2 is achieved with respect to the minimal value that would be obtained assuming heat conduction as the only means of heat transfer in the liquid. Further an analytic lumped model is presented to estimate the transient average droplet temperature with an accuracy of 5% compared to the full transient computational fluid dynamics modelling.

Si Trench Around Drain (STAD) technology of GaN-DHFETs on Si substrate for boosting power performance

We report on the first measurement results to obtain over 2 kV breakdown voltage (VBD) of GaN-DHFETs on Si substrates by etching a Si Trench Around Drain contacts (STAD). Similar devices without trenches show VBD of only 650 V. DHFETs fabricated with STAD technology show excellent thermal performance confirmed by electrical measurements and finite element thermal simulations. We observe lower buffer leakage at high temperature (100°C) after STAD compared to devices with Si substrate, enabling high temperature device operation.