Vladimir Cherman

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

In-depth Raman spectroscopy analysis of various parameters affecting the mechanical stress near the surface and bulk of Cu-TSVs

This paper discusses mechanical stress measured with micro-Raman spectroscopy in the silicon substrate near Cu-Through Silicon Vias (TSV). A discussion of the relation between the observed Raman shift and the various stress tensor components is given, showing that this relation is often wrongly applied, and that in many cases the compressive stress along the vertical axis of the TSV, dominates the Raman results and hides the tensile axial component which is of most relevance for its impact on CMOS devices. The effect of measurement depth, TSV depth and density, and an oxide cap is shown. Both surface and cross-sectional results are discussed. Also a direct correlation between results from Raman measurements and electrical results from FET-arrays near a TSV is given.

Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology

This work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration.

Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. The complexity of the interconnection structures, combined with the reduced thermal spreading in the thinned dies and the poorly thermally conductive adhesives complicate the thermal behavior of a stacked die structure. The same dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die package compared to a single die package. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, a steady state and transient analysis is presented for hot spots in 3D stacked structures. For this analysis, dedicated test chips with integrated heaters and temperature sensors are used to assess the temperature profile in the different tiers of the stack and to investigate the impact of TSVs on the temperature profile. This experimental set-up is used to evaluated and improve the thermal models for the 3D stacks.

3D stacking induced mechanical stress effects

In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.

Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

3D-TSV technologies promise increased system integration at lower cost and reduced footprint. One of the most likely applications of 3D technology is the integration DRAM-on-logic. Thermal management issues are considered one of the potentially showstoppers for 3D-integration. In this paper, we present a thermal experimental and modeling characterization of a packaged DRAM on logic stack. The DRAM die is stacked to the thinned logic die (25μm) using CuSn microbumps. For the experimental characterization a dedicated logic chip with integrated heaters and sensors is used. The thermal impact of logic hot spot dissipation on the temperature profile of the DRAM and the logic die is experimentally characterized in a dedicated socket using two experimental configurations mimicking a high power and a low power configuration respectively. The use of those 2 different experimental configurations of the packaged stack allows the calibration of a detailed finite element thermal model. The calibrated thermal models are used to evaluate the impact of the effective thermal conductivity of the microbump and underfill layer and the impact of the logic die thickness on the temperature distribution in the logic and DRAM die for different cooling configurations of the die stack.

Analysis of microbump induced stress effects in 3D stacked IC technologies

Besides the stress around Cu TSVs, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting FETs through the thinned silicon die and the stress on the thin die caused by 3D stacking. We find that the FET current shifts reach over 40% due to the impact of stress. Additionaly, a FEM parametric study was performed to determine key stress reduction contributors in 3D stacks.

Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage

The effect of thermal cycling, accelerated thermal storage and long-term storage at room temperature on the performance of FEOL devices integrated together with through silicon vias (TSVs) is studied. The transistor performance is used as monitor of stress induced in the Si by the TSV. It is observed that storage at high temperatures increases the stress in the Si induced by the TSV while thermal cycling and long- term storage at room temperature decreases this stress. These stress variations are hypothesized to be due to creep of copper in the TSV.

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.

Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs

3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. The complexity of the interconnection structures, combined with the reduced thermal spreading in the thinned dies and the poorly thermally conductive adhesives complicate the thermal behaviour of a stacked die structure. The same dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die package compared to a single die package. Therefore, the thermal behaviour in a 3D-IC needs to be studied thoroughly. In this paper, a test vehicle to assess power dissipation in multiple hot spots and the thermal impact of TSVs, is presented. In this test vehicle, a stack of test chips with integrated heaters and temperature sensors is used to evaluate the steady state and transient temperature profile of multiple hot spots. With this experimental set-up, the thermal modelling of the 3D stacks is validated.