Yasuo Hidaka

A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Maximum baud rate of electrical signaling over backplanes is limited by reflection and crosstalk noise at connectors as well as ISI caused by frequency-dependent dielectric loss. A DFE is an effective circuit to alleviate ISI without amplifying noise. A multi-tap DFE is often used in order to cancel long-tail ISI [1–3]. However, multiple DFE taps may limit maximum operation speed due to analog feedback when using non-speculative taps [1,2], or increase power and area exponentially when using multiple speculative taps [3]. Another approach is a combination of a 1-tap speculative DFE to get faster speed and a linear equalizer (LE) to cancel the long-tail ISI [4,5]. Adaptive control is challenging when combining LE and DFE, because the relationship between LE and DFE must be taken into account [5], and the sign-sign-least-mean-square (SS-LMS) algorithm [7] that is commonly used in DFEs is not applicable to some types of LE, or at the cost of increased power and area for parallel signal paths in LE [6]. The zero-forcing (ZF) algorithm for analog filters [8] is applicable to any type of LE, but it needs an ADC and a large amount of logic to perform matrix multiplication. A heuristic algorithm [5] requires an eye measurement circuit, microcontroller, and control software.

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS

Standards such as OIF CEI-25G, CEI-28G and 32G-FC require transceivers operating at high data rates over imperfect channels. Equalizers are used to cancel the inter-symbol interference (ISI) caused by frequency-dependent channel losses such as skin effect and dielectric loss. The primary objective of an equalizer is to compensate for high-frequency loss, which often exceeds 30dB at fs/2. However, due to the skin effect in a PCB stripline, which starts at 10MHz or lower, we also need to compensate for a small amount of loss at low frequency (e.g., 500MHz). Figure 2.1.1 shows simulated responses of a backplane channel (42.6dB loss at fs/2 for 32Gb/s) with conventional high-frequency equalizers only (4-tap feed-forward equalizer (FFE), 1st-order continuous-time linear equalizer (CTLE) with a dominant pole at fs/4, and 1-tap DFE) and with additional low-frequency equalization. Conventional equalizers cannot compensate for the small amount of low-frequency loss because the slope of the low-frequency loss is too gentle (<;3dB/dec). The FFE and CTLE do not have a pole in the low frequency region and hence have only a steep slope of 20dB/dec above their zero. The DFE cancels only short-term ISI. Effects of such low-frequency loss have often been overlooked or neglected, because 1) the loss is small (2 to 3dB), 2) when plotted using the linear frequency axis which is commonly used to show frequency dependence of skin effect and dielectric loss, the low-frequency loss is degenerated at DC and hardly visible (Fig. 2.1.1a), and 3) the long ISI tail of the channel pulse response seems well cancelled at first glance by conventional equalizers only (Fig. 2.1.1b). However, the uncompensated low-frequency loss causes non-negligible long-term residual ISI, because the integral of the residual ISI magnitude keeps going up for several hundred UI. As shown by the eye diagrams in the inset of Fig. 2.1.1(b), the residual long-term ISI results in 0.42UI data-dependent Jitter (DDJ) that is difficult to reduce further by enhancing FFE/CTLE/DFE, but can be reduced to 0.21UI by adding a low-frequency equalizer (LFEQ). Savoj et al. also recently reported long-tail cancellation [2].

Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters

This paper analyzes the signaling and digital power overhead of pre-emphasis voltage-mode transmitters. Utilizing a shunt branch in parallel with the differential channel to implement pre-emphasis is shown to have the best overall energy-efficiency. Leveraging this technique, an efficient pre-emphasis voltage mode transmitter architecture with output amplitude control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65 nm LP CMOS implementation of this architecture dissipates ~ 10 mW from a 1.2 V supply when transmitting 10 Gb/s 200 mV differential amplitude data with 2-tap pre-emphasis, achieving 1 pJ/bit energy efficiency.

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer

Fabricated in 90nm CMOS, the chip consumes 545mW and has a pattern-balancing adaptive equalizer that is stable for any data patterns including those with a strong peak component at a single frequency. The adaptive equalizer yields a gain at fs/2 relative to fs/16 varying from -1.7 to 2.2dB for any 8B10B encoded Ethernet frames filled with a fixed data byte

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel

In multi-Gb/s wireline communications, equalizers are used to compensate for channel-induced signal distortion in order to stretch the maximum distance of transmission. Both amplitude and phase can be distorted in a channel. Amplitude distortion is a frequency-dependent attenuation due to skin effect and dielectric loss, causing inter-symbol-interference (ISI). A transmitter (TX) discrete-time pre-emphasis (PE) filter, a receiver (RX) continuous-time Linear Equalizer (LE), and an RX Decision-Feedback Equalizer (DFE) are generally used to cancel ISI. At 10Gb/s or higher data rate, equalizers for up to 33 to 39dB Nyquist loss and up to 20 to 25dB adapted loss range were reported [1–3]. On the other hand, how to compensate phase distortion is not clearly understood in practical circuit design. Theoretically, if a channel has minimum-phase-likecharacteristics, phase distortion is automatically co-equalized with amplitude distortion by a minimum-phase equalizer [4]. While this is the case for high-speed cables [5], it is not for PCB traces, because a non-minimum-phase equalizer, e.g., a PE with a pre-cursor tap, produces lower BER over a high-loss PCB channel than a minimum-phase equalizer, e.g., a PE without a pre-cursor tap. Thus the IEEE 10Gb Ethernet standard for backplanes adopted 3-tap PE with a precursor tap [6]. However, adaptive phase equalization in hardware has not been reported in the literature.

A 4-channel 3.125Gb/s/ch CMOS transceiver with 30dB equalization

A 4-channel 3.125Gb/s/ch CMOS transceiver has been developed. The receiver includes a second-order derivative analog equalizer to compensate the frequency-dependent attenuation. Equalization can be performed adaptively through monitoring the residual inter-symbol-interference. To talk with a system without receiver equalization, a multiple-tap filter for pre-emphasis is implemented in transmitter. Either analog filter or pre-emphasis is capable of 30dB equalization. Transceiver design is compatible with XAUI and 10GBASE-CX4, but extending the reach over copper cabling. Evaluation shows lower than 10/sup -12/ BER has been achieved with 30-meter AWG 24 cable.

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE

We demonstrate that a 32Gb/s transmitter with a 4-way interleaved configuration is feasible in 28nm CMOS. A bit in the data stream contributes to a 2UI-wide pulse in the output signal, eliminating the need for 2-to-1 MUXs and enabling the use of quarter-rate clocking. A 4-tap 1UI-spacing FIR filter is implemented in the transmitter to compensate for the signal loss in the signal transmission media. The output signal is compatible with conventional NRZ receivers with a DFE.

Gain-phase co-equalization for widely-used high-speed cables

Based on observation that widely-used high-speed cables have minimum-phase-like characteristics, we developed a minimum-phase equalizer, which is optimal for such cables. An analog 2/sup nd/-order derivative equalizer was employed, and our analysis showed positive coefficients are needed to make it minimum-phase. Since the equalizer is minimum-phase, phase is automatically equalized when gain is equalized enough. The equalizer was implemented in 0.11/spl mu/m CMOS technology, and measurement showed BER < 10/sup -12/ with a 40m AWG24 InfiniBand cable at 3.125Gbaud.

A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS

A low-power pre-emphasis voltage mode transmitter architecture with output swing control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only ~10mW from a 1.2V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-tap pre-emphasis, achieving 1pJ/bit energy efficiency.

Design Consideration of 6.25 Gbps Signaling for High-Performance Server

As network data rate increases rapidly, high-speed signaling circuits for server communication pose many design challenges due to various system requirements using different interconnect mediums. This paper discusses main problems and solutions of high-speed circuits for server interconnect. Then, it presents a high-speed circuit implementation for such interconnect using 90nm CMOS technology that achieved data rate at 6.25 Gbps in a backplane environment.