Hideyuki Terane

A 100-MHz 2-D discrete cosine transform core processor

A 100-MHz two-dimensional discrete cosine transform (DCT) core processor applicable to the real-time processing of HDTV signals is described. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with sufficient accuracy to satisfy the specifications in CCITT recommendation H.261. The core integrates about 102 K transistors and occupies 21 mm/sup 2/ using 0.8- mu m double-metal CMOS technology. >

A 50 ns video signal processor

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538 k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0- mu m double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.<<ETX>>

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0- mu m CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment. >