Sadahiko Miura

High critical currents in epitaxial YBa2Cu3O7−x thin films on silicon with buffer layers

As‐deposited superconducting thin films (∼0.1 μm) of YBa2Cu3O7−x have been prepared by pulsed laser deposition on (100) Si with buffer layers of BaTiO3/MgAl2O4. X‐ray diffraction studies reveal that the films grow epitaxially with the c axis preferentially oriented normal to the substrate surface. This is confirmed by ion channeling measurements along the (100) (normal to the surface) and (110) directions of the Si substrate showing a minimum yield of 54% along the (100), and 78% along the (110) axes using 2.8 MeV He++. Preliminary transmission electron microscopy study also supports these results. The as‐deposited films have zero resistance temperatures of 86–87 K, and critical current densities of 6×104 A/cm2 at 77 K and 1.2×105 A/cm2 at 73 K. Our results indicate that the superconducting properties of the films are limited primarily by the quality and degree of epitaxal growth of the buffer layers on the silicon substrate.

A 90nm 12ns 32Mb 2T1MTJ MRAM

Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1–4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of stand-alone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time.

Epitaxial Y-Ba-Cu-O Films on Si with Intermediate Layer by RF Magnetron Sputtering

Epitaxial films of Y-Ba-Cu-O were obtained on Si substrate using epitaxial intermediate layer consisting of SrTiO3(or BaTiO3)/MgAl2O4. MgAl2O4 was epitaxially grown on Si(100) substrate by chemical vapor deposition, and then SrTiO3 or BaTiO3 was also epitaxially grown on MgAl2O4 layer by means of RF magnetron sputtering. Y-Ba-Cu-O films were prepared on SrTiO3(BaTiO3)/MgAl2O4/Si substrates by RF magnetron sputtering and their epitaxial growth was confirmed by RHEED observation and X-ray diffraction measurements. Epitaxial orientations of Y-Ba-Cu-O films varied in dependence on RF input power; lower RF power resulted in c-axis oriented film and higher RF power resulted in a-axis oriented film. Preparation of Y-Ba-Cu-O directly on MgAl2O4/Si was also studied, but only randomly oriented polycrystal film has been obtained so far. In sputter Auger depth measurement, any notable diffusion between Y-Ba-CuO film and the substrates was not observed. Resistive superconducting transitions with zero resistance at 65K on SrTiO3/MgAl2O4/Si and at 70K on BaTiO3/MgAl2O4/Si were observed.

Preparation of epitaxial ABO3 perovskite-type oxide thin films on a (100)MgAl2O4/Si substrate

Epitaxial thin films of ABO3 perovskite‐type oxides, including PbTiO3, (Pb0.90La0.10) (Zr0.65Ti0.35)0.975O3,BaTiO3, and SrTiO3, have been successfully obtained by rf magnetron sputtering on (100)Si substrate with an intermediate epitaxial layer of MgAl2O4. Only PbTiO3 grew in the tetragonal crystal structure and other materials grew in the cubic structure. The unit axis direction of the perovskite‐type oxide films was coincident with that of the underlying MgAl2O4 films. The tetragonal PbTiO3 films were a mixture of c and a domain. The preferred orientation of the tetragonal PbTiO3 film, that is c to a domain volume ratio, could be controlled by the conditions of sample cooling after the deposition. Highly c‐axis oriented films, which consisted of more than 90% c domains, were produced by cooling the sample at a high cooling rate, typically 30 °C/min, and by maintaining an rf plasma during cooling. The mechanism of the preferred orientation of PbTiO3 film has been explained by a balance of compressive str...

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cells static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJs cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of todays VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.

A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under Vdd=1V. The 1Mb chip with 2.19μm2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

As‐grown superconducting Bi‐Sr‐Ca‐Cu‐O thin films by coevaporation

Superconducting Bi‐Sr‐Ca‐Cu‐O thin films have been prepared on (100) MgO substrates at about 600 °C by coevaporation. The c‐axis lattice constant of this system was controlled to the values of 24–43 A by changing film composition. Superconducting transition temperatures of these films were affected by substrate temperature and by a post‐deposition annealing at a low temperature. The highest zero resistance temperature (Tc, zero) of the as‐grown Bi2(Sr,Ca)3Cu2Ox film was 79 K. The best Bi2(Sr, Ca)4Cu3Ox film showed an onset temperature of 105 K and Tc, zero zero of 78 K after annealing at 400 °C for 1 h.